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Integrated Gate Runner and Field Implant Terminations for Trench Devices

A technology of gate runner grooves and grooves, which is applied in the direction of semiconductor devices, electrical solid state devices, electrical components, etc., and can solve problems such as expensive manufacturing and mechanical stress/strain of semiconductor devices

Active Publication Date: 2016-01-20
FAIRCHILD SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Unfortunately, many of the known termination structures included in transistor devices can occupy a substantial portion of the device die area, can be expensive to manufacture, and can cause mechanical stress / strain within the semiconductor device

Method used

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  • Integrated Gate Runner and Field Implant Terminations for Trench Devices
  • Integrated Gate Runner and Field Implant Terminations for Trench Devices
  • Integrated Gate Runner and Field Implant Terminations for Trench Devices

Examples

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Embodiment Construction

[0014] figure 1 is a block diagram showing a semiconductor chip 192 including several regions. The semiconductor chip 192 has a floating field region 110 , a gate runner region 120 , and an active region 130 . Such as figure 1 As shown in , the gate runner region 120 is arranged between the floating field region 110 and the active region 130 .

[0015] The active region 130 may include a semiconductor device 132 . In some implementations, semiconductor device 132 may be electrically coupled to a plurality of other semiconductor devices (not shown). In some embodiments, semiconductor device 132 may be configured to operate as a single semiconductor device or to operate as a single semiconductor device in conjunction with multiple other semiconductor devices. In some implementations, semiconductor device 132 may be referred to as an active device.

[0016] In some embodiments, the semiconductor device 132 (or another semiconductor device) may be, for example, any type of po...

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PUM

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Abstract

The present invention relates to integrated gate runner and field implant terminations for trench devices. In one general aspect, an apparatus may include a plurality of trench metal oxide semiconductor field effect transistor (MOSFET) devices formed within an epitaxial layer of a substrate and a gate disposed around the plurality of trench MOSFET devices and within the epitaxial layer. Runner groove. The apparatus may also include a floating field implant defined by the well implant and disposed around the gate runner trench.

Description

technical field [0001] The present invention relates to integrated gate runners and field implant terminations for trench devices. Background technique [0002] Known transistor devices can be configured to handle relatively high currents at relatively high voltages. Such transistor device arrangements, which may be referred to as power devices, may include, for example, bipolar field effect devices including, for example, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and the like. These transistor devices can be constructed with various features, such as low on-resistance, fast switching speed, low current consumption during switching operations, relatively low capacitance inherent to various gate structures, and the like. [0003] Despite significant advances in transistor device technology, one of the limiting factors for higher current levels is breakdown voltage, especially in the edge termination region. Bec...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/10H01L29/06
CPCH01L29/0619H01L29/0696H01L29/41766H01L29/4236H01L29/42372H01L29/4238H01L29/66727H01L29/66734H01L29/7811H01L29/7813H01L27/10
Inventor 郝际发加里·多尔尼马克·里乌
Owner FAIRCHILD SEMICON CORP