A digital signal processing method
A processing method and signal technology, applied in the direction of encryption device with shift register/memory, etc., can solve the problems of inability to meet high requirements for digital signal processing and analysis, DSP cannot play, data cannot be encrypted, etc. degree of accuracy, prevention of brute-force cracking, and the effect of strict and precise time-complexity correlations
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Embodiment 1
[0020] Such as figure 1 As shown, the present invention provides a method for digitizing signals, including:
[0021] Step 1. The front-end system receives the original digitized signal "ebdaacaehfbihcebiiid" and transmits it to the DSP through the transmission system;
[0022] Step 2. On the DSP, the original digitized signal is "ebdaacaehfbihcebiiid", its basic set {a, b, c, d, e, f, g, h, I, j}, and the basic data set converted from the basic set is { 0,1,2,3,4,5,6,7,8,9};
[0023] Step 3. The basic data set corresponding to the original digitized signal is mapped to the 0th order sequence of "41300204751872418883";
[0024] Step 4. Start to process the data of order 0. For the initial basic data set {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}, the first number 4 to be processed is in The actual bit sequence in the initial basic set is 6, which is processed in reverse - counting from the back to the front, adding 0-1 to the actual bit sequence to obtain a sequential bit sequence of 5,...
Embodiment 2
[0031] Such as figure 2 As shown, at least one DSP chip is connected to the front-end system and the first synchronous dynamic random access memory;
[0032] The front-end system includes: FPGA, the second synchronous DRAM, the third synchronous DRAM, FLASH memory, A / D converter, ARM chip, power supply, USB HOST, JTAG, DM9000, RS232 and RS485, the FPGA is connected Described DSP chip, ARM chip, power supply, second synchronous DRAM and A / D converter, described ARM chip is connected described USB HOST, JTAG, DM9000, RS232, RS485, FLASH memory and the 3rd synchronous DRAM .
[0033] ARM is responsible for processing the input and output of the entire system and process management scheduling, including initial configuration settings;
[0034] FPGA is mainly responsible for the scheduling of specific sequence processing tasks and the data communication between DSP and ARM;
[0035] There can be one or more DSPs, which are generally determined according to the size of the data ...
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