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Forming method of metallic gate electrode layer

An electrode layer and metal gate technology, which is applied in the manufacturing of circuits, electrical components, semiconductor/solid-state devices, etc., can solve the problems of forming gaps in the metal gate electrode layer, and achieve the effect of easy removal and improved quality.

Active Publication Date: 2013-05-22
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology

[0012] The present invention aims to solve the problem of forming voids in the metal gate electrode layer during the process of manufacturing high-K metal gates using the prior art

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  • Forming method of metallic gate electrode layer
  • Forming method of metallic gate electrode layer
  • Forming method of metallic gate electrode layer

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Embodiment Construction

[0033] The inventors found that in the existing high-K metal gate formation process, in the process step of forming a metal gate electrode layer filling the opening on the surface of the high-K gate dielectric layer, voids are easily formed in the metal gate electrode layer, The performance of the semiconductor device is reduced, the power consumption is increased, and the reliability is reduced.

[0034] After further research, the inventor found that the high-K metal gate process includes the following steps:

[0035] Please refer to figure 1 , providing a substrate 100, the surface of the substrate 100 has a polysilicon dummy gate layer 101 and sidewalls 102 on both sides of the polysilicon dummy gate layer 101; The etch barrier layer 103 of the wall 102, the etch barrier layer 103 is silicon nitride; the surface of the etch barrier layer 103 is formed with an interlayer dielectric layer 104, and the interlayer dielectric layer is silicon oxide;

[0036] Please refer to ...

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Abstract

A forming method of a metallic gate electrode layer comprises the steps: providing a substrate, wherein a polycrystalline silicon pseudo gate electrode layer and side walls on both sides of the polycrystalline silicon pseudo gate electrode layer are arranged on the surface of the substrate; forming an etch barrier layer on the surface of the substrate, wherein the etch barrier layer is used for covering the polycrystalline silicon pseudo gate electrode layer and the side walls; forming an interlayer dielectric layer on the surface of the etch barrier layer; flattening the interlayer dielectric layer and the etch barrier layer until the polycrystalline silicon pseudo gate electrode layer is exposed; removing the polycrystalline silicon pseudo gate electrode layer, forming an opening, and forming protrusions on the side wall of the top of the opening; forming protective layers on the surfaces of the interlayer dielectric layer and the etch barrier layer, and filling the opening with the protective layers; flattening the protective layers, the interlayer dielectric layer, the etch barrier layer and the side walls with a certain thickness until the protrusions are removed; and removing the protective layers. The metallic gate electrode layer which is formed through the forming method of the metallic gate electrode layer is high in quality.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a metal gate electrode layer. Background technique [0002] With the development of integration and miniaturization of semiconductor devices, the MOS devices whose materials are the gate dielectric layer of silicon dioxide and the gate electrode layer of polysilicon have problems such as increased leakage and loss of the gate electrode layer; in order to solve the above-mentioned In order to solve the problem, the process of dielectric layer of high-K material and gate electrode layer of metal material (referred to as high-K metal gate, HKMG) has become a research hotspot. [0003] The formation process of the high-k metal gate can be divided into two types: "gate-front" process and "gate-last" process. The gate-last process can avoid the high-temperature annealing of the metal gate electrode layer and can maintain the excellent performance of the dev...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/336
Inventor 王庆玲邵群
Owner SEMICON MFG INT (SHANGHAI) CORP