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DMA controller and data readout device

A DMA controller and data technology, applied in electrical digital data processing, instruments, memory systems, etc., can solve problems such as increased CPU burden

Inactive Publication Date: 2013-05-22
MITSUBISHI ELECTRIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the memory area is large, etc., the load on the CPU when searching for data increases

Method used

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  • DMA controller and data readout device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0037] figure 1 It is a block diagram showing the configuration of a data readout device including a DMA controller according to Embodiment 1 of the present invention. This data readout device is installed, for example, in equipment (a so-called data logger) that is connected to a plurality of power conditioners in a solar power generation system and collects data related to the operating status of each power conditioner.

[0038] like figure 1 As shown, the data readout device includes CPU (Central Processing Unit, central processing unit) 10, ROM (Read Only Memory, read only memory) 20, RAM (Random Access Memory, random access memory) 30, DMA (Direct Memory Access) controller 40 , and storage medium 50 , and each component is connected to each other via bus 60 .

[0039] The CPU 10 controls the operation of the entire device including the data readout device based on various programs, data, and the like stored in the ROM 20 . The RAM 30 is used as a work memory or the lik...

Embodiment approach 2

[0055] Next, a DMA controller according to Embodiment 2 of the present invention will be described. The DMA controller of the second embodiment is also included in the same data readout device as that of the first embodiment. In addition, the same code|symbol is attached|subjected to the part common to the data reading apparatus of Embodiment 1, and it demonstrates. Figure 5 It is a block diagram showing the structure of the DMA controller 40 of this embodiment. like Figure 5 As shown, in the DMA controller 40 of this embodiment, a search data register 407 is added. Data desired by the CPU 10 (for example, a sector number) is stored in the search data register 407 .

[0056] refer to Image 6 The flow chart of FIG. 1 illustrates the procedure of data read processing executed by the DMA controller 40 of this embodiment. This data reading process is also started when a predetermined control signal is output by the CPU 10 as in the first embodiment.

[0057] First, the co...

Embodiment approach 3

[0065] Next, an embodiment of the data readout device of the present invention will be described. Figure 7 It is a block diagram showing the structure of the data readout device of this embodiment. like Figure 7 As shown, the data reading device includes CPU10, ROM20, first internal memory 31, second internal memory 32, first DMA controller 41, second DMA controller 42, external memory interface 70, and external memory 51.

[0066] The CPU 10 , ROM 20 , first internal memory 31 , second internal memory 32 , first DMA controller 41 , second DMA controller 42 , and external memory interface 70 are connected to each other via an internal bus 61 . In addition, the external memory interface 70 and the external memory 51 are connected via the external bus 62 which is a serial bus. In this embodiment, a serial flash memory is used as the external memory 51 .

[0067] The CPU 10 controls the operation of the entire device including the data readout device based on various program...

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PUM

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Abstract

A DMA controller (40) includes: a read start address register (402) for storing a read start address where readout is to be started; a read data size register (403) for storing the size of data to be read out by one readout process; an offset register (404) for storing an offset for updating the read start address after completion of the readout process; a repetition upper limit register (405) for storing an upper limit of the number of repetitions of the readout process; and a repetition counter register (406) for storing the number of repetitions of the readout process. A control unit (401) of the DMA controller (40) outputs an interrupt signal indicating that processing of the DMA controller (40) has completed when a value stored in the repetition counter register (406) reaches a value stored in the repetition upper limit register (405).

Description

technical field [0001] The present invention relates to a technique for reading data from a readable and writable storage medium using a DMA (Direct Memory Access, direct memory access) controller. Background technique [0002] For example, in the CPU of a device that uses a flash memory as a storage medium, it is necessary to appropriately perform a process of specifying a storage location (physical address) of desired data in a memory area of ​​the flash memory. However, when the memory area is large, etc., the load on the CPU when searching for data increases. Therefore, there is also known a method of causing the DMA controller to read data to reduce the load on the CPU as disclosed in Patent Document 1 and the like. [0003] In this case, the CPU sets the address to start reading (reading start address) and the size of the data to be read (for example, byte unit). When the DMA controller reads the designated number of bytes of data from the designated read start addr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28
CPCG06F13/28G06F12/00G06F13/32G06F13/34
Inventor 中田成宪久代纪之伊藤善朗小泉吉秋
Owner MITSUBISHI ELECTRIC CORP
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