Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Special instruction set processor based on scalable processor architecture and its implementation method

A technology of processor architecture and special instructions, applied in the field of electronics, can solve the problems that the four-stage pipeline structure cannot be applied to the addressing mode, is not suitable for large-scale parallel processing of processors, and does not realize floating-point arithmetic, etc., so as to overcome the single function and discomfort. For embedded applications, rich addressing modes, overcoming the effects of insufficient addressing modes and slow running speed

Inactive Publication Date: 2015-11-25
XIDIAN UNIV
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage of this patent application is that the proposed four-stage pipeline structure cannot be applied to the addressing mode of base address plus index, and this patent application does not have typical processor architecture support. In addition, this patent application does not implement floating-point arithmetic , timer and interrupt management and other commonly used functions, the function is relatively single, and it is greatly limited in practical applications
The disadvantage of this patented technology is that the whole system is too complex, consumes a lot of hardware resources, and is not suitable for large-scale parallel processing of processors.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Special instruction set processor based on scalable processor architecture and its implementation method
  • Special instruction set processor based on scalable processor architecture and its implementation method
  • Special instruction set processor based on scalable processor architecture and its implementation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0041] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0042] refer to figure 1 , The dedicated instruction set processor of the present invention includes an instruction fetch unit, a decoding unit, an execution unit, a memory access unit, a write-back unit, a pipeline control unit, a timer and an interrupt controller.

[0043] The output terminal of the instruction fetching unit is connected to the decoding unit through the instruction fetching and decoding register, and is used to access the program memory, fetch the instruction pointed to by the current program counter, provide instructions for the decoding unit, and generate the address of the next instruction to be executed ; The output terminal of the decoding unit is connected with the timer, the interrupt controller and the pipeline control unit, and the output terminal of the decoding unit is connected with the execution unit through the decoding execut...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an ASIP based on an extensible processor architecture and a realizing method thereof, which mainly solve the problem of high circuit complexity and large resource consumption in the prior art. Aiming at the extensible processor architecture after optimization, the invention adopts a five-level-pipeline realizing method, and adopts a data orientation technology and a branch non-execution strategy to solve data hazards and control hazards in pipeline treatment respectively. The ASIP comprises an instruction fetch unit, a decoding unit, an execution unit, a memory access unit, a write-back unit, a pipeline control unit, a timer and an interrupt controller. According to the ASIP and the method, the characteristics of a pipeline processor and an FPGA (field-programmable gate array) are considered sufficiently, the pipeline structure is partitioned reasonably, and the hardware resources of the FPGA are utilized to the utmost extent; and the ASIP and the method have the advantages of simple circuit design, low resource consumption, high processor performance and low power consumption, and are highly suitable for large-scale parallel processing.

Description

technical field [0001] The invention belongs to the field of electronic technology, and further relates to a special-purpose instruction set processor based on an extensible processor architecture in the field of reduced instruction set microprocessor technology and an implementation method thereof. The invention can be applied to embedded processors, especially in aerospace image processing to realize large-scale parallel processing. Background technique [0002] Application-specific instruction set processor technology is a processor specially designed for a specific application and a certain field of application. It satisfies the required performance, cost and power requirements by studying certain characteristics of the application. General-purpose processors are a balance between these two extremes. Special instruction set processors are widely used in digital signal processing, audio and video processing, image processing and other fields due to their strong specifici...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/318
Inventor 张犁李钦鹏李甫李森宋云朋石光明
Owner XIDIAN UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products