Manufacturing method of dummy gate in gate-last process
A gate-last process and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., to achieve the effect of improving reliability and expanding the filling process window
Active Publication Date: 2017-03-08
SOI MICRO CO LTD
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Problems solved by technology
Such a large-depth, small-sized rectangular gate trench poses a great challenge to the subsequent filling process of high-K and metal gate materials in terms of filling coverage, density, and uniformity in the wafer.
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[0020] The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with schematic embodiments, and a dummy gate manufacturing method in the gate-last process is disclosed. It should be noted that similar reference numerals denote similar structures.
[0021] First refer to figure 2 , sequentially forming a dummy gate material layer 20 and a hard mask material layer composed of at least one first mask layer 31 and at least one second mask layer 32 on the substrate 10, the formation method is, for example, APCVD, LPCVD, PECVD , HDPCVD and other conventional deposition methods. The substrate 10 can use various substrate materials according to the electrical performance requirements of the device, such as single crystal silicon, silicon on insulator (SOI), single crystal germanium, germanium on insulator (GeOI), or SiGe, SiC, InSb, GaAs, GaN and other compo...
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Abstract
The invention provides a production method of a false gate in back gate process. The production method includes steps: a false gate material layer and a hard mask material layer are sequentially formed on a substrate, wherein the hard mask material layer comprises a first phosphosilicate glass (PSG) mask layer and a second tetraethyl orthosilicate (TEOS) silicon oxide mask layer; the hard mask material layer is etched respectively in a dry method and a dilute hydrofluoric acid (DHF) wet method to form an up wide and down narrow hard mask picture; and the hard mask picture serves as a mask, the false gate material layer is etched in a dry method to form an up wide and down narrow false gate. According to the false gate production method, the existing vertical false gate is produced to be the up wide and down narrow regular trapezoid false gate; after the false gate is removed, a regular trapezoid groove can be formed; and therefore follow-up high K or metal gate material filling is greatly facilitated, a filling process window is enlarged, and further device reliability is improved.
Description
technical field [0001] The invention relates to a method for manufacturing a semiconductor device, more specifically, to a method for manufacturing a dummy gate in a gate-last process. Background technique [0002] With the successful application of high-K / metal gate engineering on the 45nm technology node, it has become an indispensable key modular project for the sub-30nm technology node. At present, only Intel, which adheres to the high-K / gate last route, has achieved success in mass production at 45nm and 32nm. In recent years, Samsung, TSMC, Infineon and other industry giants following the IBM industry alliance have also shifted the focus of previous development from high-K / gate first to gate last engineering. [0003] In the Gate last project, after the ion high-temperature annealing is completed, it is necessary to dig out the polycrystalline dummy gate, and then fill in high-K and metal gate materials. The process is shown in Figure 1. Such as Figure 1A As shown, ...
Claims
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IPC IPC(8): H01L21/28H01L21/283
Inventor 杨涛赵超李俊峰赵玉印卢一泓
Owner SOI MICRO CO LTD