Method for identifying short-circuit path in integrated circuit layout verification process

A technology of integrated circuits and identification methods, which is applied in the fields of electrical digital data processing, special data processing applications, instruments, etc., and can solve problems such as complex connection relationships, increased time spent, and difficulty in finding short-circuit paths.

Inactive Publication Date: 2013-07-03
北京华大九天科技股份有限公司
View PDF3 Cites 9 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Entering the era of deep sub-micron, with the increase of design scale, the scale of layout data expands rapidly, which will inevitably lead to more and more graphics of the same potential, more and more complex connection r

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for identifying short-circuit path in integrated circuit layout verification process
  • Method for identifying short-circuit path in integrated circuit layout verification process

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0011] Step (1) Initialize, read in the connection relationship between graphs, and build an undirected graph; figure 1 As shown, sequentially read in the graphic connection relationship in the layout, and construct the following figure 2 The undirected graph shown. For the storage of undirected graphs, adjacency matrix or adjacency list can be selected according to its sparseness.

[0012] Step (2) identifies the vertex corresponding to the graph where each label is located as the target point; figure 2 As shown, vertices identified as A, B, C.

[0013] Step (3) decomposes the undirected graph into independent subgraphs of a plurality of connected relations; in this method, a subgraph division algorithm based on equivalence class merging is adopted, and the following steps are performed in turn:

[0014] a) Traversing the undirected graph, numbering each vertex from small to large

[0015] b) Set the two vertices connected by each edge in the graph as an equivalence rel...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a method for identifying a short-circuit path in an integrated circuit layout verification process, belongs to the technical field of integrated circuit computer aided design, and particularly relates to the field of integrated circuit layout design rule checking (DRC) and layout versus schematic (LVS). The invention aims at providing a method for quickly searching the short-circuit path in a layout database. The problem of searching the short-circuit path in the layout database is transformed into the problem of the shortest path between appointed top points in an undirected graph through abstract expression, and the solution space is divided into a plurality of subspaces independent of each other according to the connectivity characteristic of the undirected graph, so that the algorithm complexity of problem solving is lowered; and meanwhile, the multi-point breadth-first shortest path search algorithm is adopted according to the characteristics of large data volume and complex connection relation in integrated circuit design, so that the required storage space is smaller and the running efficiency is higher relative to the general search algorithm.

Description

technical field [0001] The invention relates to a method for identifying short-circuit paths in integrated circuit layout verification, and belongs to the technical field of computer-aided design of integrated circuits, especially involving design rule checking (DRC) of integrated circuit layouts and consistency between layouts and schematic diagrams Sex Check (LVS) field. Background technique [0002] With the continuous shrinking of the device feature size of integrated circuits, the continuous improvement of integration, and the increasingly complex structure and process, the scale of the layout database is also increasing. At present, the size of the layout database in the common GDSII format is on the order of GB, and some large designs even reach TB. order of magnitude. With the expansion of chip scale, the design rules that need to be verified in each stage of integrated circuit design are also increasing. Among them, the design rule check (DRC) of the integrated ci...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F17/50
Inventor 王志明王国庆丁丰庆毛凌颖
Owner 北京华大九天科技股份有限公司
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap