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Timing generation circuit

A technology for generating circuits and circuits, applied to electrical components, drinking vessels, pulse counters, etc., to achieve the effect of reducing the scale of circuits

Active Publication Date: 2013-07-17
SEIKO INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, in the conventional timing generation circuit, in the case of generating eight types of output pulses with different timings, a 4-bit binary counter obtained by connecting four T flip-flop circuits and a 4-input logic element are required. decoding circuit

Method used

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no. 1 Embodiment approach

[0019] figure 1 It is a circuit diagram showing the timing generation circuit of the first embodiment.

[0020] The timing generating circuit of the first embodiment includes: a 3-bit binary counter 50 composed of three T flip-flop circuits 101 to 103, a delay circuit 201, a 3NAND circuit 202, an RS latch circuit 203, a 2NOR circuit 204, and an inverter circuit. 205 and decoding circuit 401.

[0021] The clock signal input terminal CLK is connected to the input terminal of the binary counter 50 . The input terminal SYS is connected to the reset terminal of the binary counter 50 and the terminal RX of the RS latch circuit 203 via the delay circuit 201 and the inverter circuit 205 . The reset terminal of the binary counter 50 is commonly connected to the reset terminals RX of the T flip-flop circuits 101 to 103 . The output terminal of the binary counter 50 is connected to the decoding circuit 401 and the 3NAND circuit 202 . The output terminal of the 3NAND circuit 202 is c...

no. 2 Embodiment approach

[0030] In the first embodiment, eight types of output pulses with different timings are generated by a binary counter composed of a 3-bit T flip-flop circuit and a decoding circuit composed of 3NAND and 3NOR, but the number of output pulses that can be generated is not limited to 8 types. For example, by adding a D flip-flop circuit to the first embodiment, nine types of output pulses with different timings can be generated.

[0031] First, the configuration of the timing generating circuit of the second embodiment will be described. Figure 4 A circuit diagram of the timing generating circuit of the second embodiment is shown.

[0032] The timing generating circuit of the second embodiment includes: a binary counter 50, a delay circuit 201, a 3NAND circuit 202, an RS latch circuit 203, a 2NOR circuit 301, a 3NOR circuit 302, a D flip-flop circuit 303, a 3NOR circuit 304, and an inverting circuit 305. , 306 and decoding circuit 401.

[0033] The clock signal input terminal C...

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Abstract

The timing generation circuit includes a binary counter constituted of three T-flip-flop circuits, and a binary state at reset of the binary counter is also used at system reset and in generation of the output pulses, to generate eight output pulses having different timings from eight binary states generated by the binary counter and including the state at the reset. At the system reset, a reset signal to the binary counter is delayed, so that an output of a decoder circuit at the reset of the binary counter is delayed. Therefore, the output of the decoder circuit is masked with a fast reset signal, so that the output of the decoder circuit at the system reset can be prevented from being reflected in an output terminal.

Description

technical field [0001] The present invention relates to a timing generating circuit, and more specifically, to a timing generating circuit mounted on a semiconductor memory device. Background technique [0002] Image 6 It is a circuit diagram showing a conventional timing generation circuit. [0003] A timing generating circuit used in an IIC interface EEPROM or the like must reset the timing generating circuit at all timings. For example, in the case of generating 8 output pulses with different timings, 9 binary states are required if the state of system reset is included. Therefore, the timing generation circuit is composed of a 4-bit binary counter obtained by connecting four T flip-flop circuits (T-FF), and a decoding circuit composed of four-input logic elements. The binary counter generates 8 binary states. The decoding circuit generates eight types of output pulses with different timings from eight types of binary states other than the binary state at the time of ...

Claims

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Application Information

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IPC IPC(8): G11C16/32
CPCH03K23/00H03K23/42A47G19/22A47G19/2205A45F3/20A45F2003/205A47G2019/2277
Inventor 今井靖
Owner SEIKO INSTR INC
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