Apparatus for realizing multi-chip Nandflash storage and read based on FPGA

Abstract

The invention discloses an apparatus for realizing multi-chip Nandflash storage and read based on FPGA. The apparatus comprises an Nandflash memory group, wherein the Nandflash memory group includes a memory array composed of a plurality of Nandflash chips and is used for storing the ADC sampling data output to Nandflash by FPGA; and an Nandflash storage and read function selector used for data reading and writing, and ID information erasing and reading of the Nandflash memory group. The above technical scheme allows the quantity of pins to be increased by times, and the data transmission bandwidth in the physical layer to be expanded, so the transmission rate is greatly raised, and the FPGA program exploitation difficulty is reduced because of the only expansion in the physical layer.

Description

technical field [0001] The invention relates to the field of analog-to-digital conversion storage technology and FPGA-based development and design, in particular to the technology of using a Nandflash chip with stable physical performance to establish a reliable expandable storage mechanism. Background technique [0002] A general memory control structure such as figure 1 As shown: the interface between the memory and the FPGA is mainly divided into address lines, data lines and control lines. The advantage of this method is that it is highly operable. When reading and writing, as long as the address is given by the FPGA, the memory can be precisely controlled. [0003] But in more specific applications, such as sonar system data acquisition, it is hoped that the memory can input data accurately and stably, and the data can be played back after the sonar system is running. So choose non-volatile memory. [0004] Non-volatile memory means that the stored data will not disap...

AI Technical Summary

Problems solved by technology

[0006] Due to the unstable physical properties of storage devices, existing solutions are prone to storage errors. Many storage controllers use DSP, single-chip microcomputers, and ARMs. It is difficult to design a high-speed storage solution for the multi-channel data storage of this system by the method; the main disadvantages of the existing method are listed in detail below:

Images