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Planar earthing method for photoelectric array device

A grounding method and photoelectric array technology, applied in the direction of electric solid state devices, electrical components, semiconductor devices, etc., can solve the problems of rising cost, high control and consistency requirements, and low yield.

Inactive Publication Date: 2013-07-31
无锡沃浦光电传感科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method requires high process control and consistency, and the control of flip chip welding is very strict, resulting in low yield and high cost.

Method used

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  • Planar earthing method for photoelectric array device
  • Planar earthing method for photoelectric array device
  • Planar earthing method for photoelectric array device

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Experimental program
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Embodiment Construction

[0030] 1. Substrate; 2. Lower contact layer; 3. Active region; 4. Upper contact layer; 5. Metal electrode layer; 6. CMOS drive circuit.

[0031] Such as Figure 8 As shown, the present invention provides a planar grounding method for photoelectric array devices, comprising the following steps:

[0032] (1) growing a lower contact layer, an active region and an upper contact layer sequentially on the substrate;

[0033] (2) Mesa patterns are formed by photolithography, and internal pixels are etched steeply;

[0034] (3) Etching a gentle slope for leading the lower electrode above the mesa;

[0035] (4) Depositing a metal electrode layer;

[0036] (5) Deposit interconnection metal;

[0037] (6) Perform flip-chip interconnection of two chips to form an electrical connection.

[0038] Such as Figure 2 to Figure 7 Shown is a schematic diagram of each step of the planarized grounding method for the photoelectric array device of the present invention.

[0039] Such as figu...

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Abstract

The invention discloses a planar earthing method for a photoelectric array device. The method comprises the following steps: (1) a lower contact layer, an active area and an upper contact layer grow on a substrate in sequence; (2) a mesa pattern is formed through photoetching, and interior pixels are etched steeply; (3) gentle slopes for leading a lower electrode to a position above a mesa are etched; (4) metal electrode layers are deposited; (5) interconnection metal is deposited; and (6) inverted interconnection of two chips is preformed to form electrical connection. According to the method, the gentle-slope mesa is formed in the position of the lower contact electrode, and the metal is deposited on the gentle slopes, so that the lower contact electrode is led onto the mesa to enable positive and negative electrodes to be located on the same plane, which is conducive to follow-up inverted interconnection.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing and relates to a planarized grounding method for photoelectric array devices. Background technique [0002] The flip-chip interconnection technology of photoelectric array devices and their corresponding drive / readout circuits has been widely used at present. Generally speaking, optoelectronic devices are double-terminal devices, including a positive electrode and a negative electrode. The two electrodes are generally located at the upper contact layer and the lower contact layer on the material structure, and the horizontal positions of the two are not consistent. On the other hand, the read / drive circuit is a standard CMOS circuit, and all its lead-out pads are located on the same plane. This creates difficulties for flip-chip interconnection. [0003] like figure 1 As shown, the existing solution is generally to deposit interconnection metal (such as In, etc.) twice on the photoele...

Claims

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Application Information

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IPC IPC(8): H01L21/60
CPCH01L2224/11
Inventor 黄寓洋塞万·拉方波罗塞刘惠春
Owner 无锡沃浦光电传感科技有限公司