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Sheet wafer defect mitigation

A flake crystal and defect technology, applied in the field of flake wafer manufacturing, can solve the problem that the downstream board is not very effective and unusable, etc.

Inactive Publication Date: 2013-07-31
MAX ERA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, these downstream plates are often less effective and sometimes unusable

Method used

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  • Sheet wafer defect mitigation
  • Sheet wafer defect mitigation
  • Sheet wafer defect mitigation

Examples

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Embodiment Construction

[0027] In an exemplary embodiment, a multi-lane furnace simultaneously forms multiple sheet wafers in a defect-mitigating manner. To this end, the furnace has means with logic for detecting and removing wafer defects from wafers grown in one lane without interrupting wafer production in other lanes. Details of illustrative embodiments are discussed below.

[0028] Figure 1A and Figure 1B Two examples of defective sheet wafers 10 are schematically shown. In a manner similar to the other sheet wafers 10, each of these sheet wafers 10 has a generally rectangular shape and a relatively large surface area on its front and rear surfaces. For example, sheet wafer 10 may have a width of about 3 inches and a length of 6 inches. Sheet wafer 10 varies in thickness and is very thin (eg, between 190 microns and 195 microns) relative to its length and width dimensions.

[0029] For example, sheet wafer 10 may be similar to the STRING RIBBON® used to form photovoltaic cells produced by...

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Abstract

A method of forming a sheet wafer melts feedstock material in a crucible that is part of a crystal growth furnace, and passes a plurality of filaments through the crucible to form a (un-separated) sheet wafers. A plurality of sheet wafers may be formed in different lanes in the crucible. One or more vision systems is used, during growth, to determine if a sheet wafer has a defective condition. If a defect is detected, then any of a variety of corrective actions may be taken, such as activating a cutting device to remove at least a portion of the sheet wafer, assessing the defect and grading a portion of the sheet wafer (e.g., for sorting based on grade), and / or producing an indicia. In a multiple-lane embodiment, a defect may be attended to in one lane while sheet growth continues in one or more other lanes.

Description

[0001] Cross References to Related Applications [0002] This patent application claims the benefit of US Provisional Patent Application No. 61 / 388,924, entitled METHOD OF MITIGATING DEFECTS WHILE FORMING A SHEET WAFER, filed October 1, 2010, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates generally to sheet wafers, and more particularly, the present invention relates to the manufacture of sheet wafers. Background technique [0004] Silicon wafers are the building blocks of a variety of semiconductor devices such as solar cells, integrated circuits, and MEMS devices. For example, Evergreen Solar Corporation of Marlboro Massachusetts forms solar cells from silicon sheet-like wafers fabricated by passing two filaments through a crucible of silicon melt. [0005] The continuous growth of silicon wafers eliminates the need to cut mass-produced silicon to form wafers. Two filaments of high temperature mat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C30B15/00C30B15/20C30B15/26C30B29/06H01L31/18
CPCH01L31/1804C30B15/007C30B29/06C30B15/26Y02E10/547C30B15/20G01N21/9506Y02P70/50
Inventor 莱奥·万格拉比克小杰拉尔德·A·辛普森苏马纳·哈马史蒂芬·亚马蒂诺
Owner MAX ERA