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Test circuit and test method of memorizer

A technology for testing circuits and testing methods, which is applied in the field of memory, can solve problems such as environmental pollution, large test time, or process fluctuations, and achieve the effect of high fault resolution and high sensitivity

Active Publication Date: 2013-09-04
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, physical defects, environmental pollution, or process fluctuations introduced in the manufacturing process of NAND-type FLASH memory will cause various faults in NAND-type FLASH memory, such as fixed faults (including Stuck-At1 faults, Stuck-At0 faults) or due to memory cell threshold voltage V TH Soft Faults Caused by Drift
However, due to the increase in storage capacity, the usual functional test consumes a lot of test time, which directly increases the test cost.

Method used

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  • Test circuit and test method of memorizer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0024] Please refer to figure 1 The test circuit of the NAND memory in this embodiment includes a signal generator 101 , a controller 102 , an actuator 103 , an oscillation ring 104 , an introduction unit 105 , and an acquisition unit 106 . Accordingly, the memory includes several memory ranks. Wherein, the controller 102 controls the signal generator 101 to generate a test signal, and the test signal can be a test pattern of all "1" or all "0", or a Checkerboard test pattern with alternate "1" and "0" (such as 01010101 or 10101010). On the one hand, the actuator 103 can write test signals into the storage array under test under the control of the controller; on the other hand, it can also read the data stored in the storage array under test under the control of the controller. The introduction unit 105 introduces a voltage signal reflecting the magnitude of the current on the measured memory column 107 into the oscillation ring 104 . The acquisition unit 106 reads the actu...

Embodiment 2

[0039] The difference between this embodiment and Embodiment 1 mainly lies in:

[0040] Such as Figure 5 As shown, the introduction unit 105 is a first PMOS transistor 501 . The oscillation ring 104 includes a cascaded NAND gate 302 and at least two inverters 303, each inverter 303 includes a second PMOS transistor 5031 and an NMOS transistor 5032 that share a control terminal and an output terminal, and the input terminal of the NMOS transistor 5032 is grounded , in a designated inverter 303: the input terminal of the second PMOS transistor 5031 is connected to the output terminal of the first PMOS transistor 501, the input terminal of the first PMOS transistor 501 is connected to the power supply voltage, and the control terminal of the first PMOS transistor 501 is connected to to the bit line of the memory column 107 under test. The output terminals of the second PMOS transistor 5031 and the NMOS transistor 5032 of the previous inverter 303 are connected with the control...

Embodiment 3

[0045] The difference between this embodiment and Embodiment 1 mainly lies in:

[0046] Such as Image 6 As shown, the introduction unit 105 is at least two first NMOS transistors 301 . The oscillating ring 104 includes a cascaded NAND gate 302 and at least two inverters 303, each inverter 303 includes a PMOS transistor 3031 and a second NMOS transistor 3032 that share a control terminal and an output terminal, and the input terminal of the PMOS transistor 3031 is connected to to the power supply voltage Vcc, the input end of the second NMOS transistor 3032 is connected to the output end of the first NMOS transistor 301, the input end of the first NMOS transistor 301 is grounded, and the control end of each first NMOS transistor 301 is connected to a corresponding measured The bit lines for column 107 are stored. The output terminals of the PMOS transistor 3031 and the second NMOS transistor 3032 of the previous inverter 303 are connected with the control terminals of the PM...

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PUM

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Abstract

The invention discloses a test circuit and a test method of a memorizer. Test signals are written in a to-be-tested memory array; an actuator reads data stored in the to-be-tested memory array; in the reading operation, an introduction unit introduces voltage signals reflecting current size of the to-be-tested memory array into an oscillation ring; work frequency of the oscillation ring is influenced by the current size of the to-be-tested memory array; and failure predication can be carried out by reading real frequency of the oscillation ring, so that the whether the to-be-tested memory array exists fixed failure or soft failure caused by shift of threshold voltage (VTH) of the memory unit can be determined; and failure position can be further determined. Since the current size change of the to-be-tested memory array caused by the failure is transferred into the change of frequency size of the oscillation ring, test precision can be higher.

Description

technical field [0001] The present application relates to the field of memory, in particular to a memory test circuit and method. Background technique [0002] Memory is a widely used integrated circuit product. FLASH memory is divided into NOR type and NAND type according to the array structure. NOR-type FLASH memory has the advantages of fast working speed, random reading and writing, and signal amplification during readout. Therefore, NOR-type FLASH memory is usually used to store programs or codes that need to be used frequently. The NAND-type FLASH memory has the advantage of being able to integrate more storage units per unit area. Therefore, the NAND-type FLASH memory is generally suitable for realizing high-density and large-capacity storage application requirements. [0003] However, physical defects, environmental pollution, or process fluctuations introduced in the manufacturing process of NAND-type FLASH memory will cause various faults in NAND-type FLASH memor...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/56
Inventor 崔小乐陈思李崇仁
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL