Formation method of transistor

Abstract

A formation method of a transistor comprises: providing a semiconductor substrate which is formed with a gate structure on the surface; carrying out ion implantation in the semiconductor substrate which is closely next to the two sides of the gate structure to form ion implantation regions which extend to the semiconductor substrate under the gate structure; removing the ion implantation regions in the semiconductor substrate with the use of a dry etching process to form openings; etching the openings with the use of a wet etching process to enable the openings to extend under the gate structure; and forming stress liner layers in the openings after the wet etching process. With the formation method of the transistor, mobility of a carrier of the transistor is enhanced, leakage current is reduced, performance of the transistor is improved and reliability is enhanced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a transistor. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing toward higher component density and higher integration in order to achieve higher computing speed, larger data storage capacity, and more functions. Therefore, gates of complementary metal oxide semiconductor (CMOS) transistors are becoming thinner and shorter than before. However, the size change of the gate will affect the electrical performance of semiconductor devices. At present, the performance of semiconductor devices is mainly improved by controlling the carrier mobility. A key element of the technology is controlling the stress in the transistor channel. For example, by properly controlling the stress and increasing the mobility of carriers (electrons in n-channel transistors, hol...

AI Technical Summary

Problems solved by technology

[0011] However, the stress of the source / drain region of the transistor with the stress liner layer formed by the prior art is limited, and the improvement of the carrier mobility of the channel region is small, resulting in a limited improvement in the performance of the formed transistor.

Images