A clock multiple selection one circuit and multiple selection one method

Abstract

The invention discloses a one-in-multiple circuit and a one-in-multiple method of a clock and belongs to the technical field of clock selection in a spaceflight electronic system. The clock one-in-multiple circuit is composed of a clock counter module, a clock selection signal generator module and a clock selector module, wherein the clock counter module, the clock selection signal generator module and the clock selector module are connected in series. A field programmable logic gate array is utilized to autonomously and reliably screen shared-frequency multi-clock sources. The clock counter module performs cycle count on each way of input clock signals, and the clock selection signal generator module detects the validity of the clock signals and outputs a clock signal selection signal. A clock selector module chooses the input clock signals and outputs one way of the clock signals. According to the one-in-multiple circuit and the one-in-multiple method of the clock, the triplication redundancy technology is utilized by a register in the circuit, the reliability of the circuit when the single event upset effect happens is enhanced, the problem of wrong detection when multi-to-one detection is performed on shared-frequency clocks in the prior art is solved, system cost, complexity and the degree of coupling are reduced, and the system efficiency and reliability are improved.

Description

technical field [0001] The invention belongs to the technical field of clock selection in aerospace electronic systems, and in particular relates to a clock multiple selection circuit and a multiple selection method realized by using a field programmable logic gate array (FPGA). Background technique [0002] Due to the high reliability requirements of aerospace technology, in order to ensure the performance of aerospace electronic systems, a 1+1 backup scheme is usually adopted. For some important units, such as FPGA clocks, their operating status is related to whether the system can work normally. Multiple backups will also be used. For the technology of selecting one of the multiple clock sources of the FPGA as an effective clock, the FPGA is required to be able to do it automatically without the assistance of other system units, so as to reduce the complexity and coupling of the system and enhance the reliability. [0003] Since the aerospace electronic system works in a...

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Problems solved by technology

[0014] To sum up, the first solution cannot independently select the clock, and requires additional system units to assist, which increases system cost, complexity and coupling, and fails to effectively improve system reliability. There are false detections in the many-to-one detection of clocks. At the same time, the above two solutions do not highlight the anti-SEU design

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