Metal capacitor for all-directional connection and layout method

Abstract

The invention discloses a metal capacitor which comprises insert finger capacitors of an odd layer and an even layer, wherein the upper part and the lower part of the odd layer comprise transverse routes and a plurality of insert fingers respectively, and the plurality of insert fingers are staggered up and down; the upper part and the lower part of the even layer comprises transverse connection routes and the plurality of insert fingers respectively, the plurality of insert fingers are staggered up and down, and continuous snake-shaped routes are also arranged between the insert fingers staggered up and down; the snake-shaped routes are positioned between the insert fingers; each of the two ends of each snake-shaped route is connected with a vertical connection line; the insert fingers of the even layer and the corresponding insert fingers of the odd layer are shifted for a unit leftwards or rightwards; and the snake-shaped routes of the even layer and the corresponding snake-shaped routes of the odd layer are shifted for a unit leftwards or rightwards. By a metal parasitic capacitance effect, the stacking area of adjacent metal layers is enlarged, a capacitor as large as possible can be obtained in a limited area, and the unit area metal capacitor is effectively expanded.

Description

technical field [0001] The invention relates to metal capacitor design in integrated circuit layout design, in particular to a metal capacitor for omnidirectional connection and a layout method. Background technique [0002] In layout design, in order to reduce the influence of noise, it is sometimes necessary to lay capacitors with a large area. [0003] With the advancement of technology and the improvement of integration, the parasitic capacitance between metal lines is getting larger and larger. For signals, this is not a good phenomenon, but it can be used to produce stable capacitance, not affected by voltage, and in Metal capacitors that are easy to implement in the process. Since the size of the parasitic capacitance is proportional to the adjacent area connected to metals with different polarities, how to increase the contact area becomes an important consideration in the design of metal capacitors. [0004] Invention patent application CN03120243.8 discloses a mu...

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Problems solved by technology

[0004] Invention patent application CN03120243.8 discloses a multi-layer forked metal capacitor structure, see figure 1 , the problem of this patent is that it only pays attention to the capacitive effect between metals in the same layer, and ignores the mutual influence between the upper and lower metal layers. Since the capacitance of the metal capacitor is proportional to the overlapping area of ​​two metals with different polarities, therefore , when the overlapping area of ​​metals with different polarities between the upper and lower layers is greatly reduced compared with the parallel structure, the efficiency of forming metal capacitors is also greatly reduced. From a theoretical point of view, for most processes, the upper and lower layers of this structure The highest interlayer capacitance can only reach 1 / 6 of the capacitance value of our proposed capacitance structure

Moreover, the problem of process deviation mentioned in the patent, because the process deviation will have a more obvious impact on the metal of the same layer, making the upper and lower metal layers into a vertical structure does not play a big role in eliminating the process deviation. The cost of sacrificing capacity value is not worth the loss

[0005] Invention patent CN200610119286.0 discloses a metal capacitor in a CMOS / BiCMOS process, which has problems: the structure is too complicated, and the 45-degree angle is not supported in many processes

Moreover, in the design of large-area metal capacitors, the problem of irregular laying area and too large area is often encountered, which is not a small workload for layout design. Therefore, how to simplify and simplify when forming large-area capacitors Splicing, how to reusability issues are increasingly prominent

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