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A method and device for converting a clock signal into a digital signal in a phase-locked loop

A clock signal and digital signal technology, applied in the field of phase-locked loop, can solve the problems of complex delay circuit and low delay accuracy, and achieve the effect of simple circuit and small size

Active Publication Date: 2016-11-02
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the embodiments of the present invention is to provide a method and device for converting a clock signal into a digital signal in a phase-locked loop, so as to solve the problems of low delay accuracy and complex delay circuits in the prior art

Method used

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  • A method and device for converting a clock signal into a digital signal in a phase-locked loop
  • A method and device for converting a clock signal into a digital signal in a phase-locked loop
  • A method and device for converting a clock signal into a digital signal in a phase-locked loop

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Embodiment 1

[0048] Such as figure 1 Shown is a flow chart of a method for converting a clock signal to a digital signal in a phase-locked loop provided by an embodiment of the present invention, and the method includes:

[0049] In step S101, the digital-to-time converter receives a clock signal output by an oscillator.

[0050] In the embodiment of the present invention, both the digital-to-time converter and the oscillator are devices in the phase-locked loop. The first step is that the digital-to-time converter receives the clock signal output by the oscillator through oscillation, and the clock signal is the phase-locked loop input signal.

[0051] In step S102, the digital-to-time converter first delays the clock signal through a delay control word.

[0052] In the embodiment of the present invention, the delay control word is the delay control signal. In the present invention, the clock signal is delayed for the first time by adding the delay control signal, that is, the first del...

Embodiment 2

[0072] Such as Figure 5 Shown is a structural diagram of the device for converting a clock signal to a digital signal in a phase-locked loop provided by an embodiment of the present invention. For convenience of description, only the parts related to the embodiment of the present invention are shown, including:

[0073] The clock signal receiving unit 501 is used for the digital time converter to receive the clock signal output by the oscillator.

[0074] In the embodiment of the present invention, both the digital-to-time converter and the oscillator are devices in the phase-locked loop. The first step is that the digital-to-time converter receives the clock signal output by the oscillator through oscillation, and the clock signal is the phase-locked loop input signal.

[0075] The first delay unit 502 is used for the digital time converter to first delay the clock signal received by the clock signal receiving unit 501 through the delay control word.

[0076] In the embodi...

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Abstract

The invention is suitable for the field of phase-lock loops, and provides a method and a device for converting clock signals to digital signals in a phase-lock loop. The method comprises the following steps: a digit time converter receives the clock signals output by an oscillator; the digital time converter conducts first time delay for the clock signals through delay control words by the digit time converter; a time digit converter conducts second time delay for the clock signals subjected to the first time delay, and converts the clock signals subjected to the second time delay to the digital signals. According to the device, the clock signals input into the phase-lock loop is subjected to the time delay through the delay control words; the controlling for the accuracy of delay time is realized by presetting the number of the delay control words; the clock signals subjected to the time delay is converted to the digital signals by converting; therefore, the accuracy of the delay control words for the clock signals is allowed to be far more better than the time delay of a bumper, and a circuit of the delay control words is simple, and small in size.

Description

technical field [0001] The invention belongs to the field of phase-locked loops, and in particular relates to a method and a device for converting a clock signal into a digital signal in a phase-locked loop. Background technique [0002] When the phase-locked loop system converts the clock signal into a digital signal, a buffer (such as an inverter) is usually used to delay the clock signal, and the delay accuracy of a single buffer is very low. [0003] The prior art proposes to use a vernier delay chain to delay the clock signal in the phase-locked loop system. Using a delay chain can make the clock signal in the phase-locked loop system achieve any delay accuracy, but it needs to use two delay chains of similar size, which requires a larger circuit area, circuit complexity and greater power. consumption. Contents of the invention [0004] The purpose of the embodiments of the present invention is to provide a method and device for converting a clock signal into a digi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/08
Inventor 周盛华
Owner HUAWEI TECH CO LTD