Unlock instant, AI-driven research and patent intelligence for your innovation.

Transistor and method for forming the transistor

A transistor and semiconductor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as prolonging etching time, and achieve the effect of improving mobility

Active Publication Date: 2016-03-16
SEMICON MFG INT (SHANGHAI) CORP
View PDF7 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method also needs to etch away more semiconductor substrate material, prolonging the etching time

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Transistor and method for forming the transistor
  • Transistor and method for forming the transistor
  • Transistor and method for forming the transistor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0053] In order to generate greater stress on the channel region, thereby further increasing the mobility of carriers and improving the performance of the transistor, an embodiment of the present invention provides a transistor and a method for forming the transistor, even if the source The doped stress layer of the drain and the drain is close to the channel region, which increases the volume of the stress layer and prevents the bottom area of ​​the stress layer from being too small or even sharp corners, thereby improving the performance of the transistor.

[0054] In order to make the above objects, features and advantages of the present invention more comprehensible, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemente...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a transistor and a method for forming the same. The transistor comprises a semiconductor substrate, a gate structure disposed on the upper surface of the semiconductor substrate, grooves disposed in the semiconductor substrate and at the two sides of the gate structure, a source disposed in the groove at one side of the gate structure, and a drain electrode disposed in the groove at the other side of the gate structure, wherein each groove comprises a first portion and a second portion, the first portion is connected with the upper surface of the semiconductor substrate, and the second portion is connected with the first portion in a penetrating manner and extends below the gate structure. The source and the drain electrode are not only close to a channel region but also have larger volume. When doped stress layers are utilized as the source electrode and the drain electrode, more manifest stress effects are exerted on the channel region and the carrier mobility is further improved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a transistor and a method for forming the transistor. Background technique [0002] In the existing semiconductor manufacturing process, the introduction of stress can change the lattice parameters of silicon materials, thereby changing its energy gap and carrier mobility, so it is becoming more and more common to improve the electrical properties of transistors by introducing stress layers means. [0003] U.S. Patent No. US7569443B2 discloses a method of improving the performance of transistors by using Embedded SiGe technology, that is, forming a SiGe layer in the area where the source and drain electrodes need to be formed, and then doping The impurities form the source and drain of the transistor. Due to the lattice mismatch (Lattice Mismatch) in the two-phase interface (Interphase) of silicon and silicon germanium, the silicon germanium layer will exert stress on the channel ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/08H01L29/78H01L21/336
Inventor 何有丰
Owner SEMICON MFG INT (SHANGHAI) CORP