Method for forming stress layer in stress memorization technique

Abstract

The invention provides a method for forming a stress layer in a stress memory technology. Grid electrode side walls are manufactured to cone-shaped side walls, and the horizontal width of each cone-shaped side wall gradually becomes larger in the direction perpendicular to the direction of a semiconductor base. The problems that a cavity exists in the stress layer between two grid structures due to too small intervals between the top ends of the two adjacent PMOS grid structure and NMOS grid structure, and then the device performance is affected are solved without affecting the follow-up ion implantation process.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a stress layer in stress memory technology. Background technique [0002] In the semiconductor manufacturing process, especially when manufacturing CMOS (Complementary Metal-Oxide-Semiconductor, Complementary Metal-Oxide-Semiconductor) devices, it is known that in order to improve the performance of CMOS, stress technology is usually used to induce stress on the trench of the MOS transistor. road area. [0003] In the prior art, a typical process for providing stress to CMOS devices is called Stress Memorization Technique (SMT), and its general steps include: providing a semiconductor substrate with an NMOS region and a PMOS region; NMOS and PMOS gates and gate sidewall layers on both sides of the gate are formed on the NMOS and PMOS regions of the NMOS and PMOS regions; a stress layer formed by inherently strained materials is formed on the substr...

AI Technical Summary

Problems solved by technology

In the actual application of SMT technology manufacturing process, such as figure 1 As shown, when forming the stress layer 7, such as a silicon nitride layer with tensile stress, due to the shrinkage of the overall feature size of PMOS1 and NMOS2, the distance between the PMOS gate 3 and the NMOS gate 4 is also reduced, and due to The gates 3 and 4 are respectively formed with gate sidewalls 5 and 6, so that as the adjacent PMOS and NMOS gate structures are too close, the deposition rate of the stress layer 7 at the corner position of the adjacent gate structure is greater than The deposition rate at other positions, therefore, will cause the stress layer 7 formed at the corners of the adjacent PMOS and NMOS transistor gate structures to be too thick, and affect the deposition of the stress layer between the PMOS and NMOS transistor gate structures, thereby causing Appears between adjacent PMOS and NMOS gates as figure 1 The void A shown in the figure will lead to uneven stress in the subsequent process and affect the performance of the device. If only the width of the gate sidewall layer in the gate structure is reduced, it will have an adverse impact on the subsequent ion implantation process.

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