Parameterization BCH (broadcast channel) error-correcting code parallel encoding method and device

An encoding method and an error-correcting code technology, which are applied in the field of parallel encoding and devices of parameterized BCH error-correcting codes, can solve problems affecting the real-time transmission characteristics of the system and large system delays, and achieve less resource occupation and faster encoding speed Effect

Inactive Publication Date: 2013-11-20
HOHAI UNIV
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Problems solved by technology

However, if the number of bits to be encoded in the actual system is large, or the number of error correction bits is large, if this metho...

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  • Parameterization BCH (broadcast channel) error-correcting code parallel encoding method and device
  • Parameterization BCH (broadcast channel) error-correcting code parallel encoding method and device
  • Parameterization BCH (broadcast channel) error-correcting code parallel encoding method and device

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Embodiment

[0051] The generator polynomial matrix of BCH(4320,4096,12) is The bit width of parallel encoding is 64 bits. The design goal is to encode 64 bits of information input in parallel in each clock cycle at the same time, and complete the encoding of 4096 bits of data information within 64 clock cycles. The detailed steps are as follows figure 2 As shown, where data(m,n) represents the n-th bit data in the m-th clock cycle during encoding; parity_tem is a temporary variable of the check digit, and function generate_gf() is a function used to generate a polynomial matrix. t_g_r(m,n) is An element of the matrix, parity_bit is the check matrix generated, with a total of 156 bits. t_g_r(155,155)*parity_temp represents the logical operation of the temporary variable of the check digit and the generating matrix. The specific process is as follows:

[0052] 1) The 64-bit information bits are shifted into the upper 64 bits of parity_temp in the same clock cycle, and logic operation...

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Abstract

The invention discloses a parameterization BCH (broadcast channel) error-correcting code parallel encoding method and device. The method comprises the following steps of determining three variable parameters such as the error-correctable bits t, bit width p of the parallel encoding and length k of data information bit, solving a generation polynomial matrix, wherein the number of times of the generation polynomial matrix g(X) is (n-k); carrying out the logic operation for a temporary variable of a check bit and the generation polynomial matrix, and finally outputting a complete encoding module described through a verilog HDL (hardware description language) language. The generated encoding module is high in encoding speed and less in occupied resource. The encoding module utilizes one generation matrix to realize the parallel encoding function and is finally solved through a series of operation according to the generation polynomial of the BCH code. The method and the device are applicable to the application with long code word, high encoding speed and capability for continuously enhancing the error correcting capacity of the error-correcting code.

Description

technical field [0001] The invention relates to the technical field of circuits and information processing in the subject of electronic information, in particular to a parallel coding method and device of a parameterized BCH error correction code. Background technique [0002] Error-correcting code technology is one of many channel coding technologies, and its purpose is to make the data information to be transmitted completely and correctly transmitted to the receiving end of the information. Throughout the entire development process of error-correcting code technology, with the rapid development of coding theory knowledge and large-scale integrated circuit technology, the application range of error-correcting code technology has become wider and wider. At present, it has been widely used in digital systems; for example , digital communication systems, data collection and data storage, as well as mobile phones, digital cameras, digital players, solid state drives, etc. in o...

Claims

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Application Information

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IPC IPC(8): H03M13/15
Inventor 李东新周桑彦
Owner HOHAI UNIV
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