MOS tube and its forming method

Abstract

A method for forming a MOS transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate is covered with a stress liner layer, the surface of the stress liner layer is covered with an epitaxial semiconductor layer, the surface of the epitaxial semiconductor layer is provided with an insulating layer, and the inner layer of the insulating layer is Having a first gate structure through its thickness and sidewalls located on the sidewalls of the first gate structure; removing the first gate structure, the epitaxial semiconductor layer corresponding to the first gate structure and the stress liner layer, forming an exposed An opening on the surface of the semiconductor substrate; forming a voltage control layer at the bottom of the opening, the voltage control layer is flush with the surface of the stress liner layer; forming an epitaxial intrinsic layer on the surface of the voltage control layer in the opening, and the epitaxial intrinsic layer and the epitaxial semiconductor The surface of the layer is flush; a second gate structure is formed on the surface of the epitaxial intrinsic layer of the opening, and the second gate structure is flush with the surface of the insulating layer. In the embodiment of the present invention, the process for forming the MOS transistor is simple, and the threshold voltage of the MOS transistor is low.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a MOS tube and a forming method thereof. Background technique [0002] The forming method of the MOS tube in the prior art includes: [0003] Please refer to figure 1 , providing a semiconductor substrate 100, the surface of the semiconductor substrate 100 is covered with an insulating film 101, the surface of the insulating film 101 is covered with a polysilicon film 103, and the surface of the polysilicon film 103 has a photoresist layer 105; [0004] Please refer to figure 2 , using the photoresist layer 105 as a mask to etch the polysilicon film and insulating film until the semiconductor substrate 100 is exposed, forming a polysilicon layer 103a and an insulating layer 101a, and the polysilicon layer 103a is located on the insulating layer 101a surface; [0005] Please refer to image 3 After the insulating layer 101 a and the polysilicon layer 103 ...

AI Technical Summary

Problems solved by technology

[0007] However, the threshold voltage of the MOS tube formed by the prior art is relatively high, and the performance of the MOS tube still needs to be improved

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