Manufacturing method for semiconductor device

Abstract

Provided is a manufacturing method for a semiconductor device. The method comprises: forming a stacked gate structure on a substrate; depositing a dielectric material layer on the substrate and the stacked gate structure; performing main etching to etch the dielectric material layer to form a side wall, and leaving residues of the dielectric material layer on the substrate; and performing over-etching to remove the residues of the dielectric material layer. According to the provided manufacturing method for the semiconductor device, instead of using a silicon oxide etching barrier layer, a two-step etching by using an etching gas containing helium is performed so that while the damage to the substrate is reduced, the process complexity is also reduced, and besides, the threshold voltage can be optimized, the EoT can be effectively reduced, and the gate-control capability and the drive current can be increased.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically, to a sidewall etching method. Background technique [0002] In VLSI manufacturing, dielectric spacers need to be made before the lightly doped drain (LDD) implantation process to prevent source-drain implantation of a larger dose from being too close to the channel to cause source-drain breakthrough, resulting in device failure and reduced yield. [0003] The current mainstream 65nm or even 45nm sidewall manufacturing process is: before the lightly doped drain (LDD) implantation process, first deposit or thermally grow a layer of silicon dioxide film, such as rapid thermal oxidation (RTO) growth Silicon dioxide on the left and right is used as a subsequent etching barrier to protect the substrate, especially the interface between the source and drain regions close to the channel region, from damage, so as to avoid the increase of defect densit...

AI Technical Summary

Problems solved by technology

In particular, the current sidewall etching technology is generally based on Ar-based gas, which is easy to cause damage to the substrate under the condition of nanoscale devices

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