Method and apparatus for preparing polysilazane on a semiconductor wafer

Abstract

A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided.

Description

technical field [0001] The present invention generally relates to the technical field of semiconductors, and more specifically relates to a method and a device for preparing polysilazane on a semiconductor wafer. Background technique [0002] According to integrated circuit design, shallow trench isolation technology has many advantages compared with local oxidation of silicon (LOCOS) in terms of manufacturing process and electrical isolation, so it has become one of the mainstream technologies after the era of line width less than 0.25 microns. [0003] Typically, shallow trench isolation (STI) is used to separate and isolate active regions on a semiconductor wafer from each other. These STIs have historically been formed by etching the trenches, overfilling the trenches with a dielectric such as oxide, and then removing any excess dielectric with a process such as chemical mechanical polishing (CMP) or etching to remove the dielectric located outside the trenches. This di...

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Problems solved by technology

[0005] However, the reactions of trisilylammonia, oxygen and ammonia under plasma treatment are very violent, so the appearance of defects in polysilazanes such as voids is usually unavoidable

These defects often lead to isolation failures for near-nanoscale linewidths

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