Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Static random access memory in embedded germanium silicon process and write-in redundancy improving method

An embedded germanium-silicon, static random technology, used in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., can solve the problems of small equivalent resistance and low write redundancy, and achieve increased equivalent resistance, improved hole mobility, and improved write redundancy

Active Publication Date: 2014-02-12
SHANGHAI HUALI MICROELECTRONICS CORP
View PDF6 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the SRAM in the existing embedded silicon germanium process, the equivalent resistance of the pull-up transistor is small, which in turn leads to a small write margin (Write Margin) of the SRAM

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Static random access memory in embedded germanium silicon process and write-in redundancy improving method
  • Static random access memory in embedded germanium silicon process and write-in redundancy improving method
  • Static random access memory in embedded germanium silicon process and write-in redundancy improving method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0021] In order to illustrate the technical content, structural features, achieved goals and effects of the present invention in detail, the following will be described in detail in conjunction with the embodiments and accompanying drawings.

[0022] see figure 1 , figure 1 Shown is a schematic diagram of an equivalent circuit for writing SRAM in the embedded silicon germanium process of the present invention. Write margin (Write Margin) is an important parameter to measure the writing performance of SRAM cells in the embedded SiGe process. In the equivalent circuit for writing SRAM in the embedded silicon germanium process, it is assumed that the first node 1 stores data at a low potential (that is, the stored data is "0"), and the second node 2 stores data It is a high potential (that is, the stored data is "1"), non-limiting enumeration, for example, writing a high potential to the first node 1, writing a low potential to the second node 2, before the writing action, The...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A static random access memory in the embedded germanium silicon process comprises a silicon-based substrate, an NMOS device, a PMOS device and a pull-up transistor. The grid electrode of the PMOS device is arranged on the silicon-based substrate, a source electrode area and a drain electrode area of the PMOS device are arranged at the position, on the two sides of the grid electrode, in the silicon-based substrate respectively, and embedded germanium silicon is arranged in the source electrode area and the drain electrode area of the PMOS device. The pull-up transistor is a PMOS semiconductor, the grid electrode of the pull-up transistor is arranged on the silicon-based substrate, and a source electrode area and a drain electrode area of the pull-up transistor are arranged at the position, on the two sides of the grid electrode, in the silicon-based substrate respectively. According to the static random access memory, the embedded germanium silicon is arranged in the source electrode area and the drain electrode area of the PMOS device, so that pressure stress of the PMOS device in the channel direction is increased, and then hole mobility is improved; no embedded germanium silicon is arranged in the source electrode area and the drain electrode area of the pull-up transistor, so that the pressure stress of the pull-up transistor in the channel direction is reduced, carrier mobility is reduced, equivalent resistance of the pull-up transistor is increased, and then write-in redundancy of the static random access memory is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a static random access memory in an embedded silicon germanium process and a method for improving write redundancy. Background technique [0002] As an important product in semiconductor memory, Static Random Access Memory (SRAM) in the embedded silicon germanium process has been widely used in high-speed data exchange systems such as computers, communications, and multimedia. [0003] Generally, the layout of the SRAM in the embedded silicon germanium process below 90nm includes three levels of active regions, polysilicon gates, and contact holes, and control transistors are respectively formed on the layout areas, and the control transistors is an NMOS device; a pull down transistor (Pull Down MOS), the pull down transistor is an NMOS device; a pull up transistor (Pull Up MOS), the pull up transistor is a PMOS device. However, in the SRAM in the existing embedded silico...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11H01L29/08H01L21/8244H10B10/00
Inventor 俞柳江
Owner SHANGHAI HUALI MICROELECTRONICS CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com