Integrated circuit layout structure and integrated chip with laser trimming technology
A technology of integrated circuits and layout structures, applied in circuits, electrical components, electrical solid devices, etc., can solve the problem of fuses affecting the performance of peripheral circuits, and achieve the effect of improving quality and efficiency and improving yield
Active Publication Date: 2016-11-02
广东德赛矽镨技术有限公司
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Problems solved by technology
If the layout design of the integrated circuit is unreasonable, the performance of the peripheral circuit may be affected because the fuse cannot be blown or the fuse is excessively burned during laser trimming.
Method used
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[0015] In order to facilitate the understanding of those skilled in the art, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0016] Such as figure 1 As shown, the integrated circuit layout structure of the present invention includes a substrate 1 and a well region 2, a silicide blocking region (SAB) 3, a first metal layer 4, and a second The metal layer 5, and on the substrate 1, a doped region 6 is provided on the periphery of the well region 2 and the silicide prevention region 3, and the doped region 6 is embedded in the substrate 8 to surround the well region 2 and the silicide prevention region 3 in a ring shape ; The first metal layer 4 covers the well region 2, the silicide blocking region 3 and the doped region 6. Among them, the second metal layer 5 and the first metal layer 4 are electrically connected, the fuse pattern 41 is arranged on the first metal layer 4, and the fuse and fuse are arr...
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The invention relates to an integrated circuit layout structure and an integrated chip with a laser trimming process. The layout structure includes a substrate and a well region, a silicide stop region, a first metal layer, and a second metal layer sequentially arranged on the substrate, and doping is arranged on the periphery of the well region and the silicide stop region on the substrate. region; the first metal layer covers the well region, the silicide stop region and the doped region. Wherein, the second metal layer is electrically connected to the first metal layer, a fuse pattern is arranged on the first metal layer, and fuses are arranged on the second metal layer, and connection lines between the fuses and other circuits in the integrated circuit are arranged on the second metal layer. The integrated chip is made according to the layout structure of the present invention. The design of the layout structure of the invention is reasonable, which can improve the quality and efficiency of chip production and ensure the reliability of the chip.
Description
Technical field [0001] The invention belongs to the field of integrated circuit design, and specifically refers to an integrated circuit layout structure with a laser trimming process and a corresponding integrated circuit chip. Background technique [0002] The voltage divider function of resistance is widely used in analog circuits, and some circuits have high requirements for voltage and current accuracy, reaching more than ±10%. The resistance is affected by the fluctuation of process parameters in the process of manufacturing by integrated circuit technology, and the accuracy is often below ±20%, which seriously affects the electrical performance of the resistance. In order to eliminate the influence of resistance deviation on the electrical performance parameters of the circuit, the integrated chip adopts the method of connecting metal fuse and resistor network in parallel to adjust the resistance value. When the metal fuse is connected in parallel at both ends of the resis...
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IPC IPC(8): H01L27/02H01L23/525
Inventor 陈唯一熊力嘉
Owner 广东德赛矽镨技术有限公司