Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Chip concurrent test system

A technology of chips and chip arrays, applied in the field of chip co-testing systems, can solve the problems of increased test costs and high costs, and achieve the effect of reducing test costs, reducing expensive costs, and being easy to implement

Active Publication Date: 2014-03-12
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
View PDF10 Cites 8 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Similarly, in order to conduct large-scale wafer-level reliability testing and evaluation of new products, it is also necessary to use a high number of probe cards for simultaneous testing, but new products and existing mass-produced products have different process conditions. Therefore, the probe card of the new product is different from the probe card used in mass production, so in the prior art, it is necessary to make a new set of probe card for the same test for the new product, and the cost of this probe card is generally More expensive, so it will increase the cost of testing
Moreover, when the process of new products is different, the probe cards also need to be different, which further increases the cost of testing.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Chip concurrent test system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0016] Such as figure 1 As shown, it is a schematic diagram of the chip simultaneous testing system of the embodiment of the present invention; the chip simultaneous testing system of the embodiment of the present invention includes:

[0017] A module board 1, the module board 1 is a module-level printed circuit board; a chip placement position is provided on an area of ​​the module board 1, and the chip placement position is used for placing multiple chip arrays.

[0018] Welding pad one 2 is formed on the periphery of the chip placement position, and the position and quantity of the welding pad one 2 are set according to the position and quantity of the welding pad two 4 of the chip 3 to be tested, and the welding pad one 2 is used for Connect with the pad 2 4 .

[0019] The chip to be tested 3 is placed on the chip position by bonding, the chip to be tested 3 is a bare chip formed by cutting a wafer, and the bonding pad one 2 and the bonding pad two 4 are directly connecte...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a chip concurrent test system comprising a module plate, and one area of the module plate is provided with a chip containing position; a bonding pad 1 is formed around the chip containing position; tested chips are placed on the chip containing position through a bonding method; the bonding pad 1and a bonding pad 2 are directly in bonding connection through a gold wire; a plurality of tested chips are placed on the chip containing position to form a chip array structure; the module plate is provided with a selector used for selecting the tested chips; a gold finger is used to add testing signals. The chip concurrent test system needs no probe card and probe bench, is wide in application range, simple in structure, and can improve test evaluation efficiency.

Description

technical field [0001] The invention relates to wafer testing of semiconductor integrated circuits, in particular to a chip simultaneous testing system. Background technique [0002] In the prior art, the wafer chip co-testing system must use the co-testing probe card. When developing and running the wafer testing system, especially the large-scale co-testing system, it is necessary to make a special co-testing probe card. , the wafer can only be tested after the same test probe card is confirmed to be correct. [0003] Similarly, in order to conduct large-scale wafer-level reliability testing and evaluation of new products, it is also necessary to use a high number of probe cards for simultaneous testing, but new products and existing mass-produced products have different process conditions. Therefore, the probe card of the new product is different from the probe card used in mass production, so in the prior art, it is necessary to make a new set of probe card for the same...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G01R31/28G01R1/04
Inventor 辛吉升桑浚之
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products