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Preparation method of germanium-on-insulator goi structure

A technology of insulator and stacked structure, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of high threading dislocation density and poor quality, and achieve the reduction of threading dislocation density and the depth of implantation. Better control and attenuation of lattice mismatch effects

Active Publication Date: 2016-01-20
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0009] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for preparing a germanium-on-insulator GOI structure, which is used to solve the problem of high threading dislocation density and poor quality in the GOI structure prepared in the prior art. question

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[0046] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] see Figure 1 to Figure 6 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arb...

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Abstract

The invention provides a preparation method for a GOI (germanium on insulator) structure. The preparation method comprises a first step of providing an SOI (silicon on insulator) substrate, and forming a SiO2 protection layer on the surface of top layer silicon; a second step of performing ion implantation from the front of the SiO2 protection layer, and enabling the injection depth to reach the top layer silicon; a third step of removing the SiO2 protection layer, and performing epitaxial growth of a SiGe layer on the surface of the top layer silicon; a fourth step of forming a Si cap layer on the surface of the SiGe layer; a fifth step of enabling the structure obtained in the fourth step to be subject to germanium concentration, and forming a laminated structure which sequentially comprises a back substrate, a buried oxide layer, a Ge layer and a SiO2 layer; and a sixth step of etching off the SiO2 layer on the surface of the laminated structure so as to obtain the GOI structure. Ion implantation is performed on an SOI substrate in advance, the SiGe layer is subject to epitaxy, and germanium concentration is performed; in the germanium concentration annealing process, ions injected in the top layer silicon weakens lattice mismatch between Si and SiGe, stress is offset and released, the penetrating dislocation density of a final GOI material is reduced, and the high-quality GOI structure is obtained.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing and relates to a method for preparing a germanium-on-insulator GOI structure. Background technique [0002] As the most widely used semiconductor material, silicon has many advantages. 1) The earth's reserves of silicon are large, so the cost of raw materials is low. 2) After 60 years of development, the purification process of silicon has reached the highest level of human beings. 3)Si / SiO 2 The interface of can be obtained by oxidation, which is perfect. An extremely perfect interface can be obtained by the post-annealing process. 4) The doping and diffusion process of silicon has been studied extensively, and there is a lot of previous experience. The disadvantage of silicon materials is that the electron and hole migration speed of silicon itself will hardly meet the needs of higher performance semiconductor devices in the future. Due to the low dielectric constant of silicon o...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762
CPCH01L21/02664H01L21/7624
Inventor 张苗陈达薛忠营王刚郭庆磊叶林狄增峰
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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