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Method for forming shallow-trench isolation structure

A technology of isolation structure and shallow trench, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problem of line width loss in the active area, achieve small loss of line width, reduce water vapor diffusion rate, and reduce oxidation Reduced effect

Inactive Publication Date: 2014-03-26
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
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Problems solved by technology

[0004] The formation method of the shallow trench isolation structure in the prior art will cause the loss of the line width of the active region

Method used

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  • Method for forming shallow-trench isolation structure
  • Method for forming shallow-trench isolation structure
  • Method for forming shallow-trench isolation structure

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Embodiment Construction

[0025] Known from the background technology, please continue to refer to figure 1 , in the prior art, after the shallow trench isolation structure 101 is treated with water vapor annealing, since water vapor can diffuse to reach Si / SiO 2 Interface, under high temperature, water vapor in Si / SiO 2 The surface will undergo an oxidation reaction with Si, resulting in the loss of the line width of the active region 102 , and the line width of the active region 102 is reduced from D1 before annealing to D2 after annealing, which affects the subsequent fabrication of devices in the active region 102 .

[0026] The inventors of the present invention designed three groups of comparative experiments to study the oxidation thickness of silicon material by annealing process under different annealing process conditions in the same annealing device. Please refer to figure 2 , Experiment Ⅰ used only dry annealing; Experiment Ⅱ used water vapor annealing first and then dry annealing; Exper...

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Abstract

The invention relates to a method for forming a shallow-trench isolation structure. The method comprises the following steps: providing a semiconductor substrate, and forming a trench in the semiconductor substrate; forming a liner layer in the trench, wherein the liner layer covers the side wall and the bottom of the trench; filling the whole trench, in which f the liner layer is formed, with oxides; sequentially conducting water vapor annealing, low-pressure annealing and dry annealing on the oxides; conducting planarization processing on the oxides. According to the method for forming the shallow-trench isolation structure, the line width loss of an active region is small.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a shallow trench isolation structure. Background technique [0002] In the shallow trench isolation (STI: Shallow Trench Isolation) manufacturing process, due to the high-density plasma (HDP: High-density Plasma) has good filling ability, better deposition film characteristics and higher yield, it has always been used Considered the preferred process for shallow trench isolation fill. However, with the continuous development of integrated circuit technology, the aspect ratio (AR: Aspect Ratio) of shallow trench isolation is getting larger and larger. At the sub-65nm node, the traditional high-density plasma filling technology has gradually been unable to meet the requirements of processes and devices. requirements. [0003] High Aspect Ratio Process (HARP: High Aspect Ratio Process) is a shallow trench isolation structure filling process proposed for...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/324H01L21/762
CPCH01L21/76224
Inventor 何有丰何永根
Owner SEMICON MFG INT (SHANGHAI) CORP
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