Packaging test method

Abstract

The invention discloses a packaging test method. The packaging test method includes the following steps that a semiconductor packaging unit is provided, wherein the semiconductor packaging unit comprises a packaging adhesive body, a lead frame and a plurality of cutting lines, and a plurality of semiconductor packaging components are defined by the cutting lines on the semiconductor packaging unit and are respectively provided with a plurality of external connection terminals; the lead frame is cut along the cutting lines to electrically insulate the semiconductor packaging components; the semiconductor packaging unit is placed on a bearing wafer; a probe card is made close to the semiconductor packaging unit placed on the bearing wafer and a plurality of probe terminals of the probe card are made to make contact with the external connection terminals respectively so that the semiconductor packaging components can be tested; semiconductor packaging components with abnormal test results are marked; the semiconductor packaging components are made monomeric, and the semiconductor packaging components marked as abnormal are removed.

Description

technical field [0001] The present invention relates to a testing method, and in particular to a packaging and testing method of a semiconductor element. Background technique [0002] In order to obtain information on the pros and cons of the process at any time during the manufacturing process of semiconductor package components, multiple test keys (test keys) are specially designed on the semiconductor package components, and these test keys are then connected through test terminals and subjected to various tests , to monitor the pros and cons of each stage of the process. [0003] After the semiconductor element is covered with encapsulant and before electroplating, each chip on the lead frame is electrically short-circuited. Therefore, if you want to test with a semiconductor package unit that has not been singulated (Singulation), you must first complete its Electrical isolation between chips. [0004] Compared with the testing method of singulated wafers, the testing...

AI Technical Summary

Problems solved by technology

Existing test systems are mostly suitable for leaded packaging structures, such as: Small Outline Package (Small Outline Package) and Quad Flat Package (QFP), etc., but for leadless packaging structures, such as: Small Outline No-Lead (SON) and Quad FlatNo-lead (QFN), etc., have difficulties in the process of chip electrical isolation

In addition, in traditional package testing, the test system needs to prepare corresponding pick-up equipment and carrying fixtures for different package structure sizes, which requires additional processes or the purchase of expensive equipment and fixtures, which has a huge impact on production costs and time. kind of waste

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