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A charge pump circuit and memory

A charge pump and circuit technology, applied in the semiconductor field, can solve problems such as system power supply jitter, and achieve the effect of preventing jitter from occurring

Active Publication Date: 2016-04-13
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The technical problem solved by the technical solution of the present invention is how to prevent the problem of system power supply jitter caused by the high driving capability of the charge pump circuit, so as to improve the system stability

Method used

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  • A charge pump circuit and memory
  • A charge pump circuit and memory
  • A charge pump circuit and memory

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0047] This embodiment provides a method such as image 3 The charge pump circuit 10 shown can be applied to various types of memories, including: a first node 300, a second node 301, a first charge pump unit 302, and a second charge pump unit 303. The charge pump circuit of this embodiment can generate programming voltages and erasing voltages according to memory operation requirements.

[0048] Continue to refer image 3 The first node 300 is connected to the first input signal PROGEN, and the second node 301 is connected to the second input signal ERSEN.

[0049] The first input signal PROGEN is actually a signal for controlling the charge pump circuit to generate the above-mentioned programming voltage, even if the charge pump circuit generates the enable signal of the programming voltage; it can be set when the first input signal PROGEN is at a high level, The charge pump circuit enters a working state of generating a programming voltage. When the first input signal PROGEN is ...

Embodiment 2

[0074] This embodiment provides a method such as Figure 4 The charge pump circuit 20 is shown.

[0075] reference Figure 4 The difference between the charge pump circuit 20 of this embodiment and the first embodiment is that the second type of clock signal is obtained by frequency division of the second clock signal, and the second clock signal also serves as the second clock signal. A type of clock signal.

[0076] The charge pump circuit 20 further includes: a frequency dividing unit 307.

[0077] Continue to refer Figure 4 The frequency dividing unit 307 includes a frequency dividing input terminal 370 and a frequency dividing output terminal 371. The frequency dividing input terminal 370 is connected to the second clock signal clk2, and the frequency dividing output terminal 371 is suitable for outputting a clock signal according to the second clock signal clk2. The divided second type clock signal clk12. The main function of the frequency dividing unit 307 is to obtain the ...

Embodiment 3

[0082] This embodiment provides another charge pump circuit, which is different from Embodiment 2 in that it is specifically used as Figure 5 The crossover unit shown.

[0083] Figure 5 The frequency division unit shown is specifically a frequency division unit by two. The frequency division unit is a D flip-flop and includes a frequency division input terminal 400, a frequency division clock terminal 401, a first frequency division output terminal 402, and a second frequency division unit. Frequency output terminal 403, the frequency division input terminal 400 is connected to the second frequency division output terminal 403, and the output signal of the second frequency division output terminal 403 is the inverse of the output signal of the first frequency division output terminal 402 signal.

[0084] Corresponding to the D flip-flop, the frequency dividing input terminal 400 is actually the D terminal of the D flip-flop, the frequency dividing clock terminal 401 is the CLK te...

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PUM

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Abstract

The invention relates to a charge pump circuit and a storage. The charge pump circuit comprises a first node connected with a first input signal, a second node connected with a second input signal, a first charge pump unit connected with a first clock signal and a second charge pump unit connected with a second clock signal. The first clock signal comprises a first class clock signal and a second class clock signal. The frequency of the first class clock signal is higher than that of the second class clock signal. The first charge pump unit is used for generating driving voltage according to the second class clock signal when the second input signal is an erasing signal. The second charge pump unit is used for generating erasing voltage according to the second clock signal and the driving voltage when the second input signal is the erasing signal. The circuit can solve the problem that a system power supply shakes due to the fact that the driving capacity of the charge pump circuit is high.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a charge pump circuit and a memory. Background technique [0002] With the rapid development of semiconductor technology, memories such as dynamic random access memory (Dynamic Random Access Memory, DRAM), electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), and flash memory (flash EPROM) have been widely used. When the memory is used, the memory needs to be provided with a corresponding programming voltage or erasing voltage when performing a programming operation (Program) or an erasing operation (Erase) on the memory. [0003] Usual storage includes such figure 1 The structure shown: a number of memory arrays 100 (including memory arrays 1 to L), a row decoder 101 and a charge pump circuit 102; among them, the row decoder 101 is connected to the charge pump circuit 102, and the memory is connected through th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H02M3/07G11C16/12G11C16/14
Inventor 黄明永杨光军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP