Method for manufacturing semiconductor device

Abstract

The invention provides a method for manufacturing a semiconductor device. The method comprises the steps of providing a semiconductor substrate which is provided with a virtual grid electrode structure, wherein side wall structures are arranged on the two sides of the virtual grid electrode structure, and autocollimation metal silicon compounds are formed on source / leakage areas on the two sides; etching back the side wall structures; conducting surface treatment on the side wall structures so as to form protection layers on the surfaces of the side wall structures; sequentially forming a contact hole etching stopping layer and an interlayer dielectric layer so as to cover the virtual grid electrode structure; executing the grinding process so as to enable the top of the virtual grid electrode structure to be exposed out; removing a sacrifice grid electrode layer in the virtual grid electrode structure so as to form a metal grid electrode structure; forming another interlayer dielectric layer once again so as to cover the metal grid electrode structure; forming contact holes. According to the method, when shared contact holes are formed, the side wall structures cannot be damaged by etching of the contact hole etching stopping layer, therefore, a substrate below the side wall structures cannot be etched, and the electric leakage phenomenon caused by etching is avoided.

Description

Technical field [0001] The present invention relates to a semiconductor manufacturing process, in particular to a method for forming a share contact. Background technique [0002] In the semiconductor device manufacturing process, the formation of shared contact holes is an essential step. [0003] The prior art forming a shared contact hole usually includes the following steps: First, as Figure 1A As shown, a semiconductor substrate 100 is provided. A shallow trench isolation (STI) structure 101 is formed in the semiconductor substrate 100. The shallow trench isolation structure 101 divides the semiconductor substrate 100 into an NMOS region and a PMOS region. . A dummy gate structure 102 is formed in the NMOS region and the PMOS region, respectively, sidewall structures 103 are formed on both sides of the dummy gate structure 102, and the sidewall structures 103 are made of nitride, preferably nitride silicon. An embedded silicon germanium layer 104 is formed in the source / dra...

AI Technical Summary

Problems solved by technology

[0004] Since the height of the previously formed contact hole etch stop layer 106 is equal to the height of the metal gate structure 108, overetching during the contact hole etching process will expose the metal gate structure 108 and the self-aligned metal structure. The substrate 111 between the silicides 105, and cause damage to the substrate 111, the resulting loss of substrate material will cause serious leakage phenomenon, degrading the performance of the device

Images