FPGA (Field Programmable Gate Array) based serial interface and PWM (Pulse Width Modulation) combined application IP (Intellectual Property) core

Abstract

The invention relates to an FPGA (Field Programmable Gate Array) based serial interface and PWM (Pulse Width Modulation) combined application IP (Intellectual Property) core. The FPGA based serial interface and PWM combined application IP core comprises a serial interface module, a PWM module and a connection module; the serial interface module is connected with the PWM module through the connection module; input data are received through the serial interface module; the input data are converted into timing data and duty ratio data through the connection module after calculation to be transmitted to the PWM module; PWM waves are output through the PWM module according to the timing data and the duty ratio data. Compared with the prior art, the operation is convenient, FPGA resources are saved, the user configurability is good, and the like.

Description

technical field [0001] The invention relates to an IP core of a system on a chip, in particular to an FPGA-based serial interface and PWM combined application IP core. Background technique [0002] As a programmable system-on-chip device with rich on-chip resources, FPGA has experienced more than 20 years of development, and has been widely concerned and generally welcomed by electronic engineering designers all over the world. It can not only solve the problems of miniaturization, low power consumption, and high reliability of electronic systems, but also has a short development cycle, less investment in development software, and continuous reduction in chip prices. All of these have prompted FPGAs to increasingly replace ASICs in the market; especially for small-volume, multi-variety product requirements, FPGAs have become the first choice. [0003] PWM is a pulse width modulation technology, which uses the digital output of the microprocessor to control the analog circui...

AI Technical Summary

Problems solved by technology

However, this method will occupy a large amount of resources in the FPGA, resulting in a waste of FPGA resources, and the configuration is relatively complicated. It is suitable for some occasions that require high PWM precision, and the cost is relatively high.

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