Semiconductor device and manufacturing method thereof

Abstract

Disclosed are a semiconductor device and manufacturing method thereof, the semiconductor device comprising: a semiconductor substrate, a well region in the semiconductor substrate, a sandwich structure located on the well region, a penetration resistance layer located below semiconductor fins, a front-gate stack intersecting with the semiconductor fins, and a source region and a drain region connected with a channel region provided by the semiconductor fins. The sandwich structure comprises a back-gate conductor, the semiconductor fins located on the two sides of the back-gate conductor, and respective back-gate dielectrics each isolating the back-gate conductor from the semiconductor fins; the well region is part of the conductive path of the back-gate conductor; and the front-gate stack comprises a front-gate dielectric and a front-gate conductor, and the front-gate dielectric isolates the front-gate conductor from the semiconductor fins. The semiconductor device realizes high integration and low power consumption.

Description

Technical field [0001] The present invention relates to semiconductor technology, and more specifically, to a semiconductor device including a fin (Fin) and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, it is desired to reduce power consumption while reducing the size of semiconductor devices to improve integration. In order to suppress the short channel effect due to size reduction, FinFETs formed on SOI wafers or bulk semiconductor substrates have been proposed. The FinFET includes a channel region formed in the middle of a fin of semiconductor material, and source / drain regions formed at both ends of the fin. The gate electrode surrounds the channel region at least on two sides of the channel region (ie, a double gate structure), thereby forming an inversion layer on each side of the channel. Since the entire channel region can be controlled by the gate, it can suppress the short channel effect. In order to r...

AI Technical Summary

Problems solved by technology

[0003] Despite their respective advantages, a semiconductor device that combines the advantages of both has not been proposed because of the many difficulties in forming the back gate in FinFETs.

In FinFETs based on bulk semiconductor substrates, due to the small contact area between the semiconductor fins and the semiconductor substrate, the formed back gate will cause serious self-heating effects

In FinFET based on SOI wafer, there is a problem of high cost due to the high price of SOI wafer

Moreover, the formation of the back gate on the SOI wafer requires precise control of ion implantation, through the top semiconductor layer to form the implantation region for the back gate under the buried insulating layer, resulting in difficulties in the process and low yield, and due to the impact on the trench Unintentional doping of the channel region leads to fluctuations in device performance

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