7 results about "Unintentional doping" patented technology

The invention discloses a gallium oxide enhanced transistor with a high power figure of merit and a manufacturing method of the gallium oxide enhanced transistor. The problem that enhancement of an existing gallium oxide device is difficult to achieve is mainly solved, and a Ga2O3 enhanced field effect transistor with the high power figure of merit is achieved. According to the manufacturing scheme of the device, a gallium oxide unintentional doping layer and a gallium oxide channel layer are sequentially grown on a gallium oxide substrate by adopting an MOCVD (Metal Organic Chemical Vapor Deposition) method; selectively growing P-type NiOX in a partial region under the gate, and then depositing gate metal; and sequentially manufacturing a source electrode, a drain electrode and a gate dielectric layer on the gallium oxide channel layer, and finally manufacturing a SiNx passivation layer and a field plate structure to complete the manufacturing of the gallium oxide enhanced transistor device. Half of the gate metal is located above the NiOX, and the other half of the gate metal is directly located above the beta-Ga2O3 layer, so that a Schottky junction between the metal and gallium oxide and a PN junction between the NiOX and the gallium oxide are formed. The two junctions play a role in regulating and controlling the channel at the same time, so that the power merit figure of the gallium oxide enhanced field effect transistor is effectively improved.

The invention discloses a comprehensive two-dimensional vertical structure metal-semiconductor field effect transistor and a preparation method thereof. A source electrode, a lower isolation layer, a drain electrode and an upper isolation layer which are vertically stacked are formed on the surface of a substrate, an inclined side wall is formed, a channel covers the inclined side wall, a grid electrode and the channel are self-aligned, and a semi-metal grid electrode and a semiconductor channel are in direct contact to form a Schottky junction; based on a comprehensive two-dimensional material system, the Fermi pinning effect and unintentional doping are effectively inhibited, and the performance of the device is optimized by optimizing the grid control capability and the electric contact performance; a gate dielectric layer is not arranged, so that the problems of electrical performance deterioration and the like under a limit miniature scale are avoided; the integration density of the device is improved and the research and development and manufacturing cost is controlled while excellent performance is kept; the channel length and the contact length are synchronously and accurately reduced by utilizing a side wall vertical structure; the method is applied to the industrial application fields of next-generation integrated circuit chips, high-density memories, flexible and wearable electronics and the like which break through the silicon-based physical limit.

This disclosure provides a semiconductor device and electronic device in which the drift region is made of AlN, which can improve the device's breakdown voltage or reduce the drift region thickness at the same breakdown voltage, thereby reducing on-resistance and epitaxial cost and difficulty. At least one of the following is formed between the drift region and the source metal through distributed polarization doping: an N+ type AlGaN current extension layer, a P- type body region, and an N+ type source ohmic contact region. Since the Al composition content in at least one of these three layers gradually changes away from the N++ type conductive substrate, a certain concentration of electrons or holes is induced through the polarization effect, which can increase the electron or hole concentration of the corresponding layer. That is, at least one layer is a high carrier concentration layer formed by unintentional doping, which can optimize current distribution and reduce device on-resistance. Since at least one of the above three layers is formed by distributed polarization doping, the carriers have higher mobility, avoiding the diffusion of dopants in high-temperature environments that could affect device performance.

The invention discloses a solar-blind ultraviolet light sensing, storage and calculation integrated gallium oxide phototransistor and a preparation method thereof. The solar-blind ultraviolet light sensing, storage and calculation integrated gallium oxide phototransistor comprises a substrate, and a gallium oxide unintentional doping layer with intrinsic solar-blind ultraviolet response capability and an N-type gallium oxide conducting layer are arranged on the substrate; two ends of the N-type gallium oxide conducting layer are respectively provided with a source end ion implantation heavily doped region and a drain end ion implantation heavily doped region by implanting doping ions, a source electrode and a drain electrode are respectively arranged above the source end ion implantation heavily doped region and the drain end ion implantation heavily doped region, and a gate dielectric layer is arranged above the N-type gallium oxide conducting layer. The top of the gate dielectric layer is provided with a gate. According to the device provided by the invention, the sensitivity, the response speed and the signal-to-noise ratio are improved, the system advantages of low power consumption, compact structure and function fusion are realized, and a feasible technical path is provided for constructing a new generation of solar blind ultraviolet sensing, storing and computing integrated system with high performance, low energy consumption and high reliability.

The invention relates to the technical field of semiconductor manufacturing, in particular to a light-emitting diode which comprises an unintentional doping layer, a first dielectric layer, a first n-type layer, a second n-type layer, a second dielectric layer, a light-emitting layer and a p-type layer which are sequentially stacked, the doping concentration of the first n-type layer is higher than that of the second n-type layer, and the doping concentration of the p-type layer is lower than that of the first n-type layer. The first dielectric layer and the second dielectric layer comprise an aluminum component, and the aluminum component in the first dielectric layer is higher than the aluminum component in the second dielectric layer. Therefore, the light-emitting diode can solve the problems of many internal defects, current carrier crowding and poor ESD performance, thereby improving the quality of the light-emitting diode.

The invention discloses a structure and method for improving the ESD resistance of a UVC LED device. The UVC epitaxial structure comprises an n-type semiconductor layer, an active layer and a p-type semiconductor layer, the n-type semiconductor layer comprises a first layer, a second layer and a third layer which are sequentially stacked in a specified direction, the first layer has a first Al component content, the second layer has a second Al component content, and the third layer has a third Al component content; the first layer at least comprises a first n-type doping concentration, the second layer at least comprises a second doping concentration, and the second layer at least comprises a third doping concentration; the content of the first Al component is larger than the content of the second Al component, the content of the third Al component is larger than the content of the first n-type doping concentration, the first n-type doping concentration is smaller than the second n-type doping concentration, the third n-type doping concentration is smaller than the third n-type doping concentration, and the first n-type doping concentration is low doping concentration or unintentional doping. According to the invention, from the fourth layer to the first layer in the n-type semiconductor layer, the content of the Al component corresponding to each layer is reduced first and then increased, the doping relation of each layer is controlled, and the ESD can be effectively reduced.

A high luminous efficiency LED epitaxial wafer structure belongs to the technical field of light emitting diodes, and comprises a substrate, and a buffer layer, an unintentional doping layer, an N-GaN layer, a first well layer, a second well layer, a built-in EBL layer, a quantum well light emitting layer, a P-type electron blocking layer and a P-GaN layer which are sequentially deposited on the substrate, the unintentional doping layer is a U-type GaN layer, the built-in EBL layer is an ALGaN layer, and the P-GaN layer is a P-type GaN layer; the temperature of the first well layer and the second well layer is increased in the epitaxial process, H2 is introduced into the first well layer and the H2 introduction amount of the first well layer is greater than that of the second well layer, so that the epitaxial quality of the quantum barrier is improved, and the dislocation defect is reduced; the built-in EBL layer is arranged, the built-in EBL layer is an ALGaN layer, electrons can be effectively blocked by utilizing the characteristic that the forbidden band width of AlGaN is large, and the electron utilization rate can be further improved; the interface processing layer is arranged, bottom layer derivation dislocation is eliminated through pause discontinuous barrier crystal annihilation, the lattice quality is improved, the composite luminous efficiency is improved, and finally the luminous efficiency of the product is greatly improved.