Conflict-free test scheduling method based on link distribution in NoC

A test scheduling and link technology, applied in the direction of electronic circuit testing, etc., can solve the problems of large granularity and unreasonable use of test resources, and achieve the effects of reducing test time, ensuring reliability and rational allocation

Inactive Publication Date: 2014-09-17
HEFEI UNIV OF TECH
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Problems solved by technology

This method is for regional division of nodes, the granularity

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  • Conflict-free test scheduling method based on link distribution in NoC
  • Conflict-free test scheduling method based on link distribution in NoC
  • Conflict-free test scheduling method based on link distribution in NoC

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Embodiment Construction

[0031] A method for scheduling conflict-free tests based on link allocation in a NoC, the operation steps are as follows:

[0032] Step 1: The Zoning Process

[0033] a. Use the partition initialization algorithm to initialize the network nodes, regard the nodes as squares, each area can be mapped into a rectangular area, and determine the initial size of the squares that need to be loaded into the rectangular area;

[0034] b. Use the improved box packing algorithm to schedule the initialized blocks, select the core with the longest test time and load it into the rectangular area first, and then test another rectangular area formed by the remaining bit width and the scheduled core test time , schedule the remaining cores to fill them up as much as possible; after allocation, each node belongs to a region, and each region is tested in parallel;

[0035] Step 2: Link Assignment Process

[0036] c. Merge adjacent nodes belonging to the same area, and each area contains several...

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Abstract

The invention discloses a conflict-free test scheduling method based on link distribution in NoC. The method includes the steps of dividing a network into multiple areas through an improved packing algorithm, setting a route tree for each boundary node to find a communicating route in the link distribution process, and enabling a parallel test of all the areas to be free of conflicts through a distribution link after alternative route collection information of all the sub-areas is synthesized. By means of the method, the link conflict problem of the parallel test in the network on chip is solved, test time of a chip can be effectively shortened, and test reliability is ensured.

Description

technical field [0001] The invention relates to the technical field of testing of integrated circuit chips, in particular to a method for scheduling tests without conflict based on link allocation in NoC. Background technique [0002] With the continuous reduction of the feature size of integrated circuits, in the design of large-scale and complex system-on-chip (SoC), the network-on-chip (NoC) architecture based on packet switching data transmission is due to its It has good reliability and scalability and has been widely studied. In NoC, data is forwarded in the network in the form of data packets, and a node can communicate with any other node through the network. This feature brings convenience to NoC testing. [0003] When discussing NoC test issues, we always want to minimize the extra overhead (including the number of test pins, area overhead, etc.) while minimizing the test time. Reusing the NoC network architecture as a test access mechanism (TAM) to transmit test...

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Application Information

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IPC IPC(8): G01R31/28
Inventor 欧阳一鸣杨鑫易茂祥梁华国黄正峰詹文发常郝
Owner HEFEI UNIV OF TECH
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