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SRAM type fpga refresh circuit and refresh method against single event upset

An anti-single event and circuit technology, which is applied in the field of field editable gate arrays, can solve the problems of controller instability and high circuit complexity, and achieve the effects of low power consumption, low complexity, and reduced modification complexity

Active Publication Date: 2017-01-04
CHANGCHUN INST OF OPTICS FINE MECHANICS & PHYSICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention provides an anti-single-event flipping circuit and method for reloading configuration commands and configuration data using an external controller to solve the problems of high circuit complexity and instability in the controller. SRAM type FPGA refresh circuit and refresh method

Method used

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  • SRAM type fpga refresh circuit and refresh method against single event upset
  • SRAM type fpga refresh circuit and refresh method against single event upset
  • SRAM type fpga refresh circuit and refresh method against single event upset

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specific Embodiment approach 1

[0022] Specific implementation mode 1. Combination figure 1 with figure 2 Describe this implementation mode, SRAM type FPGA refresh circuit against single event upset; including BOOT memory and SCRUB memory. The BOOT memory stores the user function modules. After power-on, the normal loading of the FPGA is completed through the data line and the control line. After the loading is completed, the FPGA refresh module will periodically control its corresponding I / O port. The control terminal is connected, so that the configuration file in the SCRUB memory is periodically loaded into the FPGA. The file stored in the SCRUB memory is a configuration file modified from the configuration file in the BOOT memory. Before loading, the file may affect the normal operation of the FPGA. The configuration command is reset or deleted, so the FPGA keeps working normally. If a single event flip occurs in the FPGA refresh module, the FPGA can be reloaded to ensure the normal operation of the FP...

specific Embodiment approach 2

[0026] Specific embodiment two, combine image 3 Describe this embodiment mode, this embodiment mode is the refresh method of the SRAM type FPGA refresh circuit of the anti-single event reversal described in specific embodiment one, and this method is realized by the following steps:

[0027] 1. Use the programmer to burn the complete configuration file to the BOOT memory, and at the same time burn the refresh configuration file to the SCRUB memory;

[0028] 2. When the system is powered on, the FPGA clears the internal configuration data and waits for the initialization to complete;

[0029] 3. The FPGA is initialized successfully, and the BOOT memory starts to configure data, and the configuration method selects the SalveSelectMap method;

[0030] Four, T 1 Milliseconds later, the BOOT memory data configuration is completed, the enable signal is set low, the chip select signal is set high, the memory is disabled, the internal address counter is cleared, and the data output...

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Abstract

The SRAM type FPGA refresh circuit and method for anti-single event flipping, relates to the field of field programmable gate array anti-single event flipping field, solves the existing SRAM type FPGA refresh circuit and method using an external controller to realize configuration commands and configuration data Reloading, there are problems such as high circuit complexity and instability in the controller. Two identical memories are used, and BOOT stores a complete configuration file. The configuration file includes the functional modules that the user wants to implement and the FGPA to achieve self-refresh. In the refresh module, SCRUB stores the edited configuration file. After the FPGA loads the first piece of memory, the refresh module starts to enter the refresh mode. By periodically reading the configuration file in the SCRUB memory, the periodic refresh under FPGA normal operation is realized. The invention effectively reduces the power consumption and circuit complexity of FPGA refreshing.

Description

technical field [0001] The invention relates to the technical field of field editable gate arrays, in particular to a refresh circuit and a method for realizing an SRAM type FPGA anti-single event reversal by using two memories. Background technique [0002] FPGAs based on static random access memory (SRAM) are widely used in the aerospace field because of their diversity and repeatability in functional configuration, small application size and short development cycle. FPGAs with integrated circuits and antifuse configurations are more susceptible to single event effects (SEE), but their outstanding advantages make them still responsible for attitude control, data transmission and image processing of aircraft in space environments. Herculean task, and gradually evolving into a trend [0003] Due to the great impact of space high-energy particles, the logic state of the internal configuration memory of SRAM FPGA is often flipped due to particle impact, that is, single event ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/413
Inventor 冯汝鹏徐伟郑晓云朴永杰王绍举徐拓奇金光
Owner CHANGCHUN INST OF OPTICS FINE MECHANICS & PHYSICS CHINESE ACAD OF SCI
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