Methods of forming barrier layers for conductive copper structures

Abstract

One illustrative method disclosed herein includes forming a trench / via in a layer of insulating material, forming a barrier layer in at least the trench / via, after forming said barrier layer, performing at least one process operation to introduce manganese into the barrier layer and thereby define a manganese-containing barrier layer, forming a substantially pure copper-based seed layer above the manganese-containing barrier layer, depositing a bulk copper-based material above the copper-based seed layer so as to overfill the trench / via, and removing excess materials positioned outside of the trench / via to thereby define a copper-based conductive structure.

Description

technical field [0001] In general, the present disclosure relates to the fabrication of precision semiconductor devices, and in particular, to various methods of forming barrier layers for forming copper-based conductive structures such as conductive lines / vias on integrated circuit products. Background technique [0002] The manufacture of advanced integrated circuits such as CPUs, storage devices, ASICs (Application Specific Integrated Circuits) and the like requires the formation of a large number of circuit components such as transistors, capacitors, resistors, etc. on a given chip area according to a specified circuit layout. During the manufacture of complex integrated circuits using technologies such as MOS (Metal Oxide Semiconductor), millions of transistors such as N-channel transistors (NFETs) and / or P-channel transistors (PFETs) are formed on on the inner base. Field effect transistors, whether considered NFET transistors or PFET transistors, generally include do...

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Problems solved by technology

Thus, the overall resistance of the conductive structure 10 is increasing as devices continue to be miniaturized

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