Unlock instant, AI-driven research and patent intelligence for your innovation.

Transistor with deep N-well implanted through the gate

A technology of transistors and logic transistors, applied in the manufacturing of semiconductor devices, electric solid state devices, semiconductor/solid state devices, etc., can solve the problems of increasing cost and cycle

Active Publication Date: 2014-09-17
TEXAS INSTR INC
View PDF9 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Separate mask level for DN well requirements increases cost and cycle time

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Transistor with deep N-well implanted through the gate
  • Transistor with deep N-well implanted through the gate
  • Transistor with deep N-well implanted through the gate

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0012] Exemplary embodiments are depicted with reference to the drawings, wherein like reference numerals are used to designate similar or equivalent elements. The illustrated order of acts or events is not to be construed as a limitation, as some acts or events may occur in a different order and / or in parallel with other acts or events. Furthermore, some of the illustrated acts or events may not be required to implement a methodology in accordance with the present disclosure.

[0013] Figure 1A After doping and annealing are completed using a fabrication method including forming a DN well 135 through a gate stack of NMOS 110 without any additional masking, including an NMOS transistor and a PMOS transistor 120 (PMOS 120 ) according to an exemplary embodiment A cross-sectional view of a portion of a CMOS IC 100 out of MOS transistors. In the illustrated embodiment, the implantation for the DN well 135 is performed at the n lightly doped drain (NLDD) / p-pocket or p-pocket mask...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a transistor with a deep N-well implanted through the gate. A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source / drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.

Description

technical field [0001] The disclosed embodiments relate to semiconductor fabrication, and more particularly, to the fabrication of complementary metal-oxide-semiconductor (CMOS) integrated circuits including deep N-wells (DN-wells), and IC devices produced thereby. Background technique [0002] With the development of metal gates on high-k gate dielectric process flow, positive bias temperature uncertainty (PBTI) has become important for n-channel MOS (NMOS). The size of PBTI is about 70% of the threshold voltage shift (ΔVt) of negative bias temperature instability (NBTI) in 20nm gate length IC manufacturing process technology. [0003] N-well reverse body bias (RBB) is traditionally used to screen static random access memory (SRAM) to effectively reduce p-channel MOS (PMOS) end-of-line (EOL) Vt degradation. SRAM is also expected to provide the capability of NMOS driver / pass-gate (PG) transistor screening for PBTI EOL. Deep N-well (DN-well) / Iso P-well implants have been pr...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8238H01L27/146
CPCH01L21/823814H01L27/0928H01L21/823892
Inventor M·南达库玛
Owner TEXAS INSTR INC