A method for detecting insufficient etching of through holes

Abstract

The invention discloses a method for detecting etching insufficiency of through holes. The method comprises the steps that a plurality of test modules are built on a semiconductor substrate, each test module simulates an SRAM device structure and comprises two simulation transmission gate transistors, two simulation pull-up transistors and two simulation pull-down transistors, the simulation transmission gate transistors, the simulation pull-up transistors and the simulation pull-down transistors are PMOS devices in an N well, and no grid electrode is formed on active areas of the simulation transmission gate transistors; a plurality of contacting holes are formed in each test module and filled with metal, and the contacting holes are at least connected with positions, corresponding to grid electrodes, in the active areas of the simulation transmission gate transistors; a metal interconnection line and a conduction through hole are formed on each contacting hole; the test modules are scanned through an electron beam defect scanner under a positive potential condition, and the etching insufficiency defects of the through holes of the test modules are detected according to the image feature pictures obtained through scanning. The method for detecting etching insufficiency of the through holes can effectively improve the capturing efficiency of the etching insufficiency defects.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a method for detecting insufficient etching of through holes. Background technique [0002] With the development of integrated circuit technology and the scaling down of critical dimensions, the etching of copper connection vias in the back-end process of semiconductor devices is insufficient (such as figure 1 Shown) and via missing defects are increasingly becoming one of the bottlenecks hindering the development of integrated circuits. For example, in the etching process of first etching the hard mask (Hard Mask Etch) and then etching the through hole (All in One Etch), the under-etching defects are often affected by the cleaning process after the hard mask etching, the via etching itself and the via etching. The common influence of the photolithography process, when some of the process windows are not optimized enough, defects will appear, which becomes a major killer...

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Problems solved by technology

[0004] Therefore, the above two detection methods for insufficient via etching have great shortcomings, and it is difficult to provide an effective reference for the optimization of the online process window

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