Improved semiconductor packaging substrate structure and manufacturing method thereof

Abstract

The invention provides an improved semiconductor packaging substrate structure. According to the improved semiconductor packaging substrate structure, the distance between substrate bonding pads is effectively shortened, and meanwhile the reliability of the substrate bonding pads is guaranteed. The improved semiconductor packaging substrate structure includes a core plate and is characterized in that the two sides of the core plate are provided with layer-adding layers; the layer-adding layers are connected with the core plate through blind holes; the bottoms of the blind holes are connected with bonding pads of the layer-adding layers on the lower surface of the core plate; the layer-adding layers on the upper surface and the lower surface of the core plate or the interiors of the layer-adding layers are provided with conducting circuits; the core plate is provided with via holes, the conducting circuits on the upper surface and the lower surface of the core plate are connected through the via holes, and hole plugging materials are arranged in the via holes; metal columns are arranged in the layer-adding layer on the upper surface of the core plate and arranged in the corresponding layer-adding layer; the metal columns are connected with an inner conducting layer; the peripheries of the metal columns are provided with layer-adding material for protection; the layer-adding layer on the lower surface of the core plate is provided with the bonding pads which are exposed out of the surface of a substrate, and the peripheries of the bonding pads are covered with solder resist ink. Meanwhile, the invention provides a manufacturing method of the improved semiconductor packaging substrate structure.

Description

technical field [0001] The invention relates to the technical field of microelectronic packaging technology, in particular to an improved semiconductor packaging substrate structure and a manufacturing method thereof. Background technique [0002] With the development of semiconductor technology, Moore's Law is approaching the edge of failure. The difficulty of IC design, wafer manufacturing, packaging and testing in the industry chain continues to increase. The pitch of the chip pads keeps getting smaller, and the development of the pitch of the undercut pads of the package substrate cannot keep up with the pace of changes in the pitch of the chip pads. How to reduce the pad pitch of the packaging substrate has become an urgent problem to be solved. [0003] A build-up process is used in the manufacturing process of the existing package substrate. After making the outermost circuit, print solder mask (Solder Mask) to form solder pads through exposure, development and oth...

AI Technical Summary

Problems solved by technology

After making the outermost circuit, print solder mask (Solder Mask) to form solder pads through exposure, development and other processes. The production of solder mask ink in the conventional process is caused by the low optical resolution and poor physical and chemical properties of the solder mask material. Problems such as large substrate pad spacing and poor reliability

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