Heterojunction bipolar transistor layout structure

Abstract

Disclosed is a heterojunction bipolar transistor layout structure including one or more heterojunction bipolar transistors, each of which comprises a base electrode, an emitter electrode and a collector electrode. A passive layer, a first dielectric layer, a collector re-distribution layer, one or more emitter copper pillars and one or more collector copper pillars are disposed above the heterojunction bipolar transistors; the passive layer comprises an emitter welding pad and a collector welding pad; the first dielectric layer is provided with one or more emitter guide holes and collector guide holes which are respectively located above the emitter welding pad and the collector welding pad; the emitter copper pillars are located on the emitter guide holes and are electrically connected to the emitter electrode; and the collector copper pillars are arranged above the collector re-distribution layer and electrically connected to the collector electrode so that the layout of the emitter copper pillars and the collector copper pillars can be flexible and the heat dissipating efficiency of components can be simultaneously improved.

Description

technical field [0001] The present invention relates to a layout structure of a heterojunction bipolar transistor, in particular to a layout structure of a heterojunction bipolar transistor having both a redistribution layer (redistribution layer, RDL) and a copper pillar. Background technique [0002] With the vigorous development of the mobile communication industry, the demand for high-performance and small-sized electronic components is also increasing. Due to the advantages of compound semiconductor heterojunction bipolar transistor integrated circuits with high power, low noise, and small size, it has been It is widely used in mobile communication electronic products. Therefore, if the performance and size of compound semiconductor heterojunction bipolar transistor circuits can be improved, product competitiveness will be effectively improved. [0003] The traditional flip-chip technology is used in the application of gallium arsenide heterojunction bipolar transistor ...

AI Technical Summary

Problems solved by technology

[0003] The traditional flip-chip technology is used in the application of gallium arsenide heterojunction bipolar transistor components. In order to improve the heat dissipation characteristics of the component, copper pillars are covered on the emitter of the component, and the original metal wire process technology is used to establish The collector and base copper pillars of the component, but due to the limitation of the minimum distance between the copper pillars in the manufacturing process, the size of the component will be limited and cannot be reduced, and the space between the copper pillars will be wasted, and the product will be greatly reduced. In addition, due to the large height difference between the emitter and the collector epitaxial layer of the heterojunction bipolar transistor, the height of the copper pillars on it is not easy to be consistent, which leads to the problem of poor contact of solder joints during chip packaging. Limiting the improvement of chip packaging yield

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