Manufacturing method of shallow trench isolation structure

A technology of isolation structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as narrow width effect, field silicon oxide intrusion, hard mask pull-back distance increase, etc., to meet the requirements of the process required effect

Inactive Publication Date: 2014-11-05
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this method has very strict requirements on the control accuracy of the pullback rate of the hard mask. In actual operation, the pullback distance of the hard mask that is in contact with the silicon substrate is often increased, resulting in silicon oxide filling in the STI trench. When the hard mask is in contact with the substrate silicon, a structure similar to the bird's break in the LOCOS process is generated, so that the field silicon oxide invades the active area, resulting in a narrow width effect

Method used

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  • Manufacturing method of shallow trench isolation structure
  • Manufacturing method of shallow trench isolation structure
  • Manufacturing method of shallow trench isolation structure

Examples

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Embodiment 1

[0033] Such as figure 1 As shown, this embodiment provides a method for manufacturing a shallow trench isolation structure, including the following steps:

[0034] S10, sequentially forming a first hard mask layer and a second hard mask layer on a semiconductor substrate;

[0035] S11, using the first hard mask layer as an etching stop layer, etching the second hard mask layer to form a shallow trench pattern;

[0036] S12, forming a third hard mask layer of a material different from that of the first hard mask layer on the first hard mask layer and the second hard mask layer;

[0037] S13, etching the third hard mask layer to form sidewalls on the sidewalls of the shallow trench pattern of the second hard mask layer;

[0038] S14, using the sidewalls and the second hard mask layer as mask layers, etching the first hard mask layer and the semiconductor substrate to form shallow trenches;

[0039] S15, performing hard mask pull-back etching on the first hard mask layer and t...

Embodiment 2

[0050] Such as image 3 As shown, this embodiment provides a method for manufacturing a shallow trench isolation structure, including the following steps:

[0051] S30, sequentially forming a first hard mask layer and a second hard mask layer on a semiconductor substrate;

[0052] S31, using the first hard mask layer as an etching stop layer, etching the second hard mask layer to form a shallow trench pattern;

[0053] S32, forming a third hard mask layer made of the same material as the first hard mask layer on the first hard mask layer and the second hard mask layer;

[0054] S33, etching the third hard mask layer to form sidewalls on the sidewalls of the shallow trench pattern in the second hard mask layer;

[0055] S34, using the sidewalls and the second hard mask layer as mask layers, etching the first hard mask layer and the semiconductor substrate to form shallow trenches;

[0056] S35, performing hard mask pull-back etching on the first hard mask layer and the secon...

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Abstract

The invention provides a manufacturing method of a shallow trench isolation structure. Through the etching rate of three hard mask layers, the pullback distance of the hard mask layer making contact with substrate silicon is guaranteed. Through the upper hard mask layer, a process window can be enlarged to form a double-layer step structure, and the process requirements of the round corner effect and insulating medium filling of a trench can be met.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a shallow trench isolation structure. Background technique [0002] A complete circuit is connected by separate devices through specific electrical pathways. In the integrated circuit manufacturing process, the devices must be isolated. If the isolation is not good, it will cause leakage and latch-up effects. Therefore, isolation technology is a key technology in the manufacture of integrated circuits. Existing isolation processes generally include local oxidation of silicon (LOCOS) and shallow trench isolation (Shallow trench isolation, STI). The LOCOS process is simple to operate, and it has been widely used in micron and submicron processes. However, the LOCOS process has a series of disadvantages. For example, the edge oxidation will form a bird's break, which will make the field silicon dioxide invade the active area, resulting...

Claims

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Application Information

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IPC IPC(8): H01L21/762
CPCH01L21/76224
Inventor 鲍宇周晓强
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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