Digital video interface decoding circuit and method

Abstract

The invention discloses a digital video interface decoding circuit and method. The decoding circuit comprises an oversampling data recovery unit, a frame synchronization unit, a channel synchronization unit, a video signal decoding unit and a video control signal filtering unit, wherein the oversampling data recovery unit receives oversampling data and recovers the oversampling data into parallel recovery data; the frame synchronization unit receives the recovery data and synchronizes frames of the recovery data according to special encoding rules of TMDS in a video blanking interval; the channel synchronization unit receives data of three chrominance channels after frame synchronization, conducts clock synchronization on the data of the three chrominance channels and then outputs the data of the three chrominance channels; the video signal decoding unit receives the synchronous data of the three channels and decodes the data in every channel at every clock into original video pixel data according to the TMDS decoding rules; the video control signal filtering unit receives video control signals and filters out spurious signals of the video control signals. The digital video interface decoding circuit decodes the TMDS oversampling data through a digital method, so the bit error rate of the video pixel data can be substantially decreased, and the stability of the video control signals can be improved.

Description

technical field [0001] The invention relates to a data decoding technology, in particular to a digital video interface decoding circuit and method. Background technique [0002] The digital video transmission standard DVI (Digital Visual Interface) or HDMI (High Definition Multimedia Interface) based on Transition Minimized Differential Signaling (TMDS) encoding has a frequency channel (channel C) for transmitting frequency signals and Three color channels (channel[0:2]) used to transmit serial data of red (R), green (G), and blue (B), each color channel uses TMDS encoding to encode 8-bit original numbers The video signal is converted into a 10-bit serial signal sequence with the minimum transmission difference. The clock channel and the line and field blanking intervals send special 10-bit data. The working clock frequency is 25-165MHz, and the data transmission rate of the color channel is Ten times the frequency signal, that is to say, there will be ten bits of serial da...

AI Technical Summary

Problems solved by technology

[0003] The bit error rate of the traditional digital video decoding circuit is too high in the process of oversampling data recovery. The traditional phase jump circuit is based on four phase cycle jumps, which will cause some oversampled data to be lost or some data to be repeated. Selection; the traditional data detection circuit is only based on the currently input 4-bit data to determine the error, left shift, right shift signal and the final recovered data, which brings a high bit error rate; the frame in the traditional digital video decoding circuit The synchronization unit performs frame synchronization once in each clock cycle, which will lead to unstable data after frame synchronization and too many burrs in the extracted video pixel enable signal DE; the traditional digital video decoding circuit does not introduce a channel synchronization unit and the video control signal filtering unit, and these two units are essential in the actual verification process, the channel synchronization unit solves the problem of data skew between each channel during high-speed transmission, and the video The signal filtering unit solves the problem that the extracted video control signal has glitches

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