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Semiconductor structures and methods of forming them

A semiconductor and patterning technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of substrate fragmentation, chip or device performance degradation, failure, etc., and achieve feature size reduction. , The thickness is uniform and dense, and the effect of avoiding the chipping of the substrate

Active Publication Date: 2017-09-22
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] However, when the TSV structure is formed by the existing technology, it is easy to cause the substrate to break, or cause the performance of the chip or device to degrade, or even fail.

Method used

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  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them
  • Semiconductor structures and methods of forming them

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Effect test

Embodiment Construction

[0039] As mentioned in the background art, when the TSV structure is formed in the prior art, it is easy to cause the substrate to break, or cause the performance of the chip or device to degrade, or even fail.

[0040] After research by the inventor of the present invention, please continue to refer to Figure 1 to Figure 3 , the conductive plug 103 is often made of copper; in addition, in order to electrically isolate the conductive plug 103 from the semiconductor substrate 100, an insulating layer is also formed between the conductive plug 103 and the semiconductor substrate 100, The material of the insulating layer is usually silicon dioxide. The thermal expansion coefficient of copper is 18ppm, the thermal expansion coefficient of silicon dioxide is 0.5ppm, and the thermal expansion coefficient of silicon substrate is 2.5ppm. Due to the difference in thermal expansion coefficient between copper, silicon dioxide and silicon substrate, and the thermal expansion coefficient o...

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Abstract

A semiconductor structure and a method for forming the same, wherein the method for forming the semiconductor structure includes: providing a substrate, the substrate having a plug region; forming an opening in the substrate, the opening surrounding the substrate A plug region; a conformal process is used to form a first dielectric layer on the sidewall surface of the opening, and the topography of the surface of the first dielectric layer is consistent with the topography of the sidewall surface of the opening; after forming the first dielectric layer, Forming a second dielectric layer on the top of the opening, the second dielectric layer seals the opening and forms a void in the opening; after forming the second dielectric layer, forming a conductive plug in the plug region of the substrate , the conductive plug is in contact with the first dielectric layer. The size of the semiconductor structure is reduced, and the cracking of the substrate can be avoided, so as to prevent the performance degradation of chips or devices.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the continuous development of semiconductor manufacturing technology, the feature size of semiconductor devices is continuously reduced, and the integration level of chips is getting higher and higher. However, the current two-dimensional packaging structure has been difficult to meet the growing demand for chip integration, so three-dimensional packaging technology has become a key technology to overcome the bottleneck of chip integration. [0003] A three-dimensional stacking technology based on through silicon vias (Through Silicon Via, TSV) is one of the existing three-dimensional packaging technologies, and the three-dimensional stacking technology based on through silicon vias is one of the main methods to improve chip integration. [0004] The three-dimensional s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L23/538
CPCH01L23/481H01L21/7682H01L21/76898H01L2924/0002
Inventor 洪中山
Owner SEMICON MFG INT (SHANGHAI) CORP
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