Spacing layer double-exposure etching method

Abstract

The invention relates to the technical field of semiconductors, and discloses a spacing layer double-exposure etching method. Before etching of an organic material layer and a semiconductor substrate, etching is performed on a spacing layer by adopting etching gas which contains CF4, Ar and Xe and is easy to form positive ion gas so that correction of the shape of the spacing layer is realized. Thickness of the spacing layer is reduced, and the shape of the spacing layer is corrected into a symmetrical or approximately symmetrical structure so that problems of uneven etching rate and over-etching caused by the spacing layer can be avoided. Meanwhile, the spacing layer is thinned via etching so that stress between the spacing layer and the organic material layer is reduced to some extent, and thus line edge roughness of the etching structure is improved and etching quality of the semiconductor substrate is enhanced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a spacer layer double exposure technology. Background technique [0002] With the continuous development of integrated circuit technology, semiconductor process nodes have gradually entered the era of 65nm and 45nm, and are moving towards more advanced 22nm and 16nm. However, as semiconductor process nodes continue to advance, the requirements for critical dimension (CD) in semiconductor device fabrication front-end process (FEOL) and back-end process (BEOL) become more and more stringent. Among them, the feature size of devices in the 65nm process has begun to be much smaller than the size of mainstream lithography. In the process of semiconductor device preparation, more and more semiconductor structures with feature sizes smaller than 65nm, or even smaller than 45nm and 32nm have begun to appear, and lithography has begun to become The bottleneck of the development of ...

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Problems solved by technology

At the same time, the uneven etching rate will also cause different etching areas to have different over-etching rates when the etching is completed, thus affecting the quality of the etched edge.

[0014] In addition, if Figure 5 As shown, the stress between the spacer layer 106 and the organic material 103 will cause the distortion of the line edge of the region 110 to be etched on the semiconductor substrate 101, thus affecting the line edge roughness of the etched structure

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