Forming method of semiconductor device

Abstract

The invention provides a forming method of a semiconductor device. The forming method of the semiconductor device comprises the following steps of providing a substrate comprising a core device area and a peripheral circuit area, wherein the core device area comprises a first PMOS (P-channel Metal Oxide Semiconductor) area and a first NMOS (N-channel Metal Oxide Semiconductor) area, and the peripheral circuit area comprises a second PMOS area and a second NMOS area; forming a first gate structure on the first PMOS area, forming a second gate structure on the first NMOS area, forming a third gate structure on the second PMOS area, and forming a fourth gate structure on the second NMOS area, wherein each gate structure comprises a gate dielectric layer and a gate positioned on the gate dielectric layer; forming a protective layer among the first to fourth gate structures and the substrate, wherein the protective layer covers the upper surface of the substrate and protects the substrate in the step of ion injection; after the first to fourth gate structures are formed, performing halo ion and LDD (Lightly Doped Drain) ion implantation on the first PMOS area and the first NMOS area, and then performing halo ion and LDD ion implantation on the second PMOS area and the second NMOS area. With the method, the mismatch value of the threshold voltage of the device is decreased.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a semiconductor device. Background technique [0002] When designing an integrated circuit, it is usually necessary to use several MOS transistors with the same electrical parameters. For example, when designing a semiconductor device that includes both a Static Random Access Memory (SRAM) and a Central Processing Unit (CPU), inside the SRAM or inside the CPU, several MOS transistors with the same electrical parameters are required. However, in actual products, the electrical parameters of the nominally identical MOS transistors in the SRAM or CPU often drift, resulting in a mismatch of the electrical parameters of the originally identical MOS transistors (Mismatch), that is, a decrease in matching characteristics, which will cause The performance degradation of SRAM or CPU, for example, will cause problems such as slowing down of SRAM storage speed, increased ...

AI Technical Summary

Problems solved by technology

[0011] In the prior art, the threshold voltage mismatch value in semiconductor devices is large

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