Forming method of semiconductor device

Abstract

The invention provides a forming method of a semiconductor device. The forming method of the semiconductor device comprises the following steps of providing a substrate comprising a core device area and a peripheral circuit area, wherein the core device area comprises a first PMOS (P-channel Metal Oxide Semiconductor) area and a first NMOS (N-channel Metal Oxide Semiconductor) area, and the peripheral circuit area comprises a second PMOS area and a second NMOS area; forming a first gate structure on the first PMOS area, forming a second gate structure on the first NMOS area, forming a third gate structure on the second PMOS area, and forming a fourth gate structure on the second NMOS area, wherein each gate structure comprises a gate dielectric layer and a gate positioned on the gate dielectric layer; forming a protective layer among the first to fourth gate structures and the substrate, wherein the protective layer covers the upper surface of the substrate and protects the substrate in the step of ion injection; after the first to fourth gate structures are formed, performing halo ion and LDD (Lightly Doped Drain) ion implantation on the first PMOS area and the first NMOS area, and then performing halo ion and LDD ion implantation on the second PMOS area and the second NMOS area. With the method, the mismatch value of the threshold voltage of the device is decreased.

Description

technical field

[0001] The invention relates to the field of semiconductors, in particular to a method for forming a semiconductor device. Background technique

[0002] When designing an integrated circuit, it is usually necessary to use several MOS transistors with the same electrical parameters. For example, when designing a semiconductor device that includes both a Static Random Access Memory (SRAM) and a Central Processing Unit (CPU), inside the SRAM or inside the CPU, several MOS transistors with the same electrical parameters are required. However, in actual products, the electrical parameters of the nominally identical MOS transistors in the SRAM or CPU often drift, resulting in a mismatch of the electrical parameters of the originally identical MOS transistors (Mismatch), that is, a decrease in matching characteristics, which will cause The performance degradation of SRAM or CPU, for example, will cause problems such as slowing down of SRAM storage speed, increased ...

Examples

Embodiment 1

[0061] refer to Figure 6 , providing a substrate 30, the substrate 30 includes a core device area A and a peripheral circuit area B; the core device area A includes: a first PMOS area A1 and a first NMOS area A2, and the peripheral circuit area B includes: The second PMOS area B1 and the second NMOS area B2.

[0062] Specifically, the semiconductor substrate 30 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI) and Silicon germanium on insulator (SiGeOI), etc. A doped region and an isolation structure may be formed in the substrate, and the isolation structure is a shallow trench isolation (STI) structure or a local oxide of silicon (LOCOS) isolation structure.

[0063] refer to Figure 7 , performing threshold voltage implantation on the surface of the substrate 30 to form a threshold voltage injection layer 35 .

[0064]The threshold voltage injection layer 35 ...

Embodiment 2

[0125] refer to Figure 21 to Figure 24 The difference between this embodiment and the first embodiment is that the substrate 30 further includes: a memory area C, and the memory area C includes: a third PMOS area C1 and a third NMOS area C2.

[0126] refer to Figure 21 , when forming the first gate structure 31 to the fourth gate structure 34 on the substrate 30, the fifth gate structure 60 is formed on the third PMOS region C1, and the sixth gate structure is formed on the third NMOS region C2 61.

[0127] For the specific method of forming the fifth gate structure 60 and the sixth gate structure 61 , please refer to the method for forming the first gate structure to the fourth gate structure in the core device region in the first embodiment. It should be noted that the dimensions of the fifth gate structure 60 and the sixth gate structure 61 are smaller than those of the first gate structure 31 and the second gate structure 32 .

[0128] According to part of the reason ...

technical field

[0001] The invention relates to the field of semiconductors, in particular to a method for forming a semiconductor device. Background technique

[0002] When designing an integrated circuit, it is usually necessary to use several MOS transistors with the same electrical parameters. For example, when designing a semiconductor device that includes both a Static Random Access Memory (SRAM) and a Central Processing Unit (CPU), inside the SRAM or inside the CPU, several MOS transistors with the same electrical parameters are required. However, in actual products, the electrical parameters of the nominally identical MOS transistors in the SRAM or CPU often drift, resulting in a mismatch of the electrical parameters of the originally identical MOS transistors (Mismatch), that is, a decrease in matching characteristics, which will cause The performance degradation of SRAM or CPU, for example, will cause problems such as slowing down of SRAM storage speed, increased ...

Examples

Embodiment 1

[0061] refer to Figure 6 , providing a substrate 30, the substrate 30 includes a core device area A and a peripheral circuit area B; the core device area A includes: a first PMOS area A1 and a first NMOS area A2, and the peripheral circuit area B includes: The second PMOS area B1 and the second NMOS area B2.

[0062] Specifically, the semiconductor substrate 30 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI) and Silicon germanium on insulator (SiGeOI), etc. A doped region and an isolation structure may be formed in the substrate, and the isolation structure is a shallow trench isolation (STI) structure or a local oxide of silicon (LOCOS) isolation structure.

[0063] refer to Figure 7 , performing threshold voltage implantation on the surface of the substrate 30 to form a threshold voltage injection layer 35 .

[0064]The threshold voltage injection layer 35 ...

Embodiment 2

[0125] refer to Figure 21 to Figure 24 The difference between this embodiment and the first embodiment is that the substrate 30 further includes: a memory area C, and the memory area C includes: a third PMOS area C1 and a third NMOS area C2.

[0126] refer to Figure 21 , when forming the first gate structure 31 to the fourth gate structure 34 on the substrate 30, the fifth gate structure 60 is formed on the third PMOS region C1, and the sixth gate structure is formed on the third NMOS region C2 61.

[0127] For the specific method of forming the fifth gate structure 60 and the sixth gate structure 61 , please refer to the method for forming the first gate structure to the fourth gate structure in the core device region in the first embodiment. It should be noted that the dimensions of the fifth gate structure 60 and the sixth gate structure 61 are smaller than those of the first gate structure 31 and the second gate structure 32 .

[0128] According to part of the reason ...

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