Single-particle turnover resistant SR latch

Abstract

The invention discloses a single-particle turnover resistant SR latch. The SR latch comprises a first signal output port, a second signal output port, a power supply, a first storage node, a second storage node, a first signal input port, a second signal input port, a third signal input port, a fourth signal input port, a first control node, a second control node, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and a tenth NMOS tube. The SR latch has the advantages of being fast in writing speed, short in delay and capable of meeting requirements of radiation-resistant high-speed integrated circuits.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits and relates to an SR latch resistant to single-event reversal. Background technique [0002] Single event effects have become one of the main reliability problems of electronic systems in the aerospace field. The single event effect affecting the SR latch is mainly the single event upset effect. Therefore, it is necessary to strengthen the SR latch against single event upset. The high-performance radiation-resistant SR latch has the characteristics of large critical charge, short flip recovery time, fast writing speed, strong driving capability, and low power consumption. The SR latches based on NAND or NOR gates mentioned in (CMOS Digital Integrated Circuits Analysis and Design, Third Edition, 248-249) written by Sung-MoKang and Yusuf Leblebici are not resistant to single event upsets, The write speed is slow, the difference between rising delay and falling delay is one gate delay,...

AI Technical Summary

Problems solved by technology

The SR latches based on NAND or NOR gates mentioned in (CMOS Digital Integrated Circuits Analysis and Design, Third Edition, 248-249) written by Sung-MoKang and Yusuf Leblebici are not resistant to single event upsets, The write speed is slow, the difference between rising delay and falling delay is one gate delay, and the driving ability is weak

Published by Jahinuzzaman (Jahinuzzaman S M, Rennie D J, Sachdev M.A soft error tolerant 10T SRAM bit-cell with differential read capability [J]. Nuclear Science, IEEE Transactions on Nuclear Science, 2009, 56(6): 3768-3773.) The mentioned Quatro-10T unit has the characteristics of high static power consumption and static noise tolerance, but the write delay is relatively large, and the storage node has a large difference in the flip recovery ability of different levels

The SR latch based on the protection gate mentioned in Duan Jian published (Duan Jian. A SEU / SET reinforced SAFF design. Journal of Xi'an University of Arts and Science: Natural Science Edition, 2011, 14(3): 80-82) can Use the redundant nodes of the upper and lower circuits to shield the level conversion of the flip node to achieve the effect of anti-SEU, but the cost in terms of area, power consumption and speed is very high

The protection gate latch proposed in Huang Ye et al. (Huang Ye, Cheng Xiulan. Design and Analysis of SEU / SET Reinforced D Flip-Flop. Semiconductor Technology, 2009, 34(1):69-72) utilizes time redundancy Technology achieves anti-SEU / SET capability, but the signal transmission speed is limited by delay, which is not suitable for high-speed circuit applications

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