Error correcting code decoder

A decoder and error-correcting code technology, applied in the field of modern digital communication systems, can solve problems such as poor configurability, limited operating speed, and inability to process in parallel, achieving low resource utilization, strong error-correcting capabilities, and reduced decoding The effect of delay

Inactive Publication Date: 2015-03-04
SUZHOU VOCATIONAL UNIV
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Problems solved by technology

[0005] In addition, the hardware can also be implemented with a DSP processor, but the configurability is poor,

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[0019] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to make a clearer and clearer definition of the protection scope of the present invention.

[0020] See figure 1 with figure 2 , The embodiment of the present invention includes:

[0021] An error correction code decoder, including:

[0022] 1) The generation process from Impulse C software to FPGA hardware:

[0023] After the Impulse C design file is preprocessed by C, the C language analysis is performed; in the C language analysis phase, the compiler determines the hardware and software processes in the application; then the initial optimization process is carried out. In the loop unwinding phase, the compiler will perform corresponding The loop is transformed into an equivalent parallel statement; after a second opti...

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Abstract

The invention discloses an error correcting code decoder. The error correcting code decoder comprises a generating flow from ImpulseC software to FPGA (Field Programmable Gate Array) hardware. The generating flow comprises the following steps: performing C preprocessing on an ImpulseC design file, and performing C language analysis; determining hardware and software processes in application by using a compiler at a C language analysis state; performing an initial optimizing flow, and converting corresponding loops into equivalent concurrent statements by using the compiler at a loop unrolling stage; performing secondary optimization to generate a simulation-supporting HDL (Hardware Description Language) file which describes various processes, flows and elements described in an ImpulseC source element; and generating FPGA decoder hardware. Through the way, the error correcting code decoder can be applied to the fields of digital television demodulation chips, high-speed broadband mobile communication systems, compressed image transmission, wireless local area networks and the like, is used for performing error control and detecting and correcting errors introduced in a signal transmission process, and is an important component for ensuring reliable transmission of data.

Description

technical field [0001] The invention relates to the field of modern digital communication systems, in particular to an error correction code decoder based on hardware / software collaborative design technology. Background technique [0002] In the error control system of a modern communication system, in addition to the LDPC code, common types of error correction codes include RS codes, Viterbi codes, convolutional codes, TURBO codes, and the like. But RS codes, Viterbi codes and convolutional codes have poor error correction performance, and their applications are limited due to the complexity of circuit implementation. [0003] Although the performance indicators of TURBO code and LDPC code are very close, there is still a certain gap, and it is not easy to implement in hardware, the system complexity is high, and it cannot be applied to all channels, so in many cases there is a tendency to be replaced by LDPC code. [0004] For the design scheme of LDPC code hardware imple...

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Application Information

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IPC IPC(8): H04L1/00H03M13/11
CPCH03M13/1102
Inventor 张培
Owner SUZHOU VOCATIONAL UNIV
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