Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Error correcting code decoder

A decoder and error-correcting code technology, applied in the field of modern digital communication systems, can solve problems such as poor configurability, limited operating speed, and inability to process in parallel, achieving low resource utilization, strong error-correcting capabilities, and reduced decoding The effect of delay

Inactive Publication Date: 2015-03-04
SUZHOU VOCATIONAL UNIV
View PDF2 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In addition, the hardware can also be implemented with a DSP processor, but the configurability is poor, and it cannot be processed in parallel, and the operating speed is limited by the clock frequency of the DSP chip

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Error correcting code decoder
  • Error correcting code decoder

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to define the protection scope of the present invention more clearly.

[0020] see figure 1 and figure 2 , the embodiment of the present invention includes:

[0021] An error correction code decoder, comprising:

[0022] 1) The generation process from Impulse C software to FPGA hardware:

[0023] Impulse C design files are preprocessed by C, and then analyzed in C language; in the stage of C language analysis, the compiler determines the hardware and software processes in the application; next, the initial optimization process is performed, and in the loop unrolling stage, the compiler will correspondingly The loop is converted into an equivalent parallel statement; after secondary optimization, a simulatable...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses an error correcting code decoder. The error correcting code decoder comprises a generating flow from ImpulseC software to FPGA (Field Programmable Gate Array) hardware. The generating flow comprises the following steps: performing C preprocessing on an ImpulseC design file, and performing C language analysis; determining hardware and software processes in application by using a compiler at a C language analysis state; performing an initial optimizing flow, and converting corresponding loops into equivalent concurrent statements by using the compiler at a loop unrolling stage; performing secondary optimization to generate a simulation-supporting HDL (Hardware Description Language) file which describes various processes, flows and elements described in an ImpulseC source element; and generating FPGA decoder hardware. Through the way, the error correcting code decoder can be applied to the fields of digital television demodulation chips, high-speed broadband mobile communication systems, compressed image transmission, wireless local area networks and the like, is used for performing error control and detecting and correcting errors introduced in a signal transmission process, and is an important component for ensuring reliable transmission of data.

Description

technical field [0001] The invention relates to the field of modern digital communication systems, in particular to an error correction code decoder based on hardware / software collaborative design technology. Background technique [0002] In the error control system of a modern communication system, in addition to the LDPC code, common types of error correction codes include RS codes, Viterbi codes, convolutional codes, TURBO codes, and the like. But RS codes, Viterbi codes and convolutional codes have poor error correction performance, and their applications are limited due to the complexity of circuit implementation. [0003] Although the performance indicators of TURBO code and LDPC code are very close, there is still a certain gap, and it is not easy to implement in hardware, the system complexity is high, and it cannot be applied to all channels, so in many cases there is a tendency to be replaced by LDPC code. [0004] For the design scheme of LDPC code hardware imple...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H04L1/00H03M13/11
CPCH03M13/1102
Inventor 张培
Owner SUZHOU VOCATIONAL UNIV
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com