High-accuracy multipath data synchronous acquisition device
A technology of data synchronization and acquisition device, applied in electrical digital data processing, instruments, etc., can solve the problems of low data transmission rate, low hardware integration, poor synchronization performance, etc., and achieve integration improvement, synchronization performance improvement, and volume reduction. small effect
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specific Embodiment approach 1
[0013] Specific implementation mode one: combine figure 1 Describe this embodiment, the high-precision multi-channel data synchronous acquisition device described in this embodiment includes GNSS equipment 1, high-precision multi-channel timing module 2, interface module 3, high-speed optical fiber serial bus 4, industrial control host 5 and large-capacity SSD 6;
[0014] Interface module 3 comprises No. 1 FPGA circuit 3-1 and No. 2 FPGA circuit 3-2, and the configuration file input / output end of No. 1 FPGA circuit 3-1 is connected to the configuration file output / input of No. 2 FPGA circuit 3-2 end;
[0015] The GPS second pulse signal output end of the GNSS device 1 is connected to the GPS second pulse signal input end of the high-precision multi-channel timing module 2, and the high-precision multi-channel timing module 2 includes n+1 TTL level second pulse signal output terminals in total , one of the output terminals is used to connect the TTL level second pulse signal ...
specific Embodiment approach 2
[0027] Specific implementation mode two: combination figure 2 Describe this embodiment, this embodiment is to further limit the high-precision multi-channel data synchronous acquisition device described in the first embodiment, in this embodiment, the high-precision multi-channel timing module 2 includes a filter circuit 2-1, FPGA control circuit 2-2, DA converter 2-3, constant temperature crystal oscillator 2-4, 50M crystal oscillator 2-5, FPGA configuration module 2-6, output expansion module 2-7, n+1 single inverter gates 2-8, n+1 optocouplers 2-9, n+1 three-state output single-channel bus buffers 2-10; wherein n is an integer greater than 2;
[0028] The signal input end of the filter circuit 2-1 is the GPS second pulse signal input end of the high-precision multi-channel timing module 2, and the filtered signal output end of the filter circuit 2-1 is connected to the capture signal input end of the FPGA control circuit 2-2, and the FPGA The voltage control signal output...
specific Embodiment approach 3
[0031]Specific embodiment three: This embodiment is a further limitation to the high-precision multi-channel data synchronous acquisition device described in embodiment two. In this embodiment, the FPGA control circuit 2-2 includes a signal capture circuit 2-2- 1. Phase difference calculation circuit 2-2-2, PID control circuit 2-2-3, 10 7 Frequency division circuit 2-2-4 and digital phase-locked loop circuit 2-2-5;
[0032] The signal input end of the signal capture circuit 2-2-1 is the capture signal input end of the FPGA control circuit 2-2, and the signal output end of the signal capture circuit 2-2-1 is connected to the signal input of the phase difference calculation circuit 2-2-2 terminal, the phase difference signal output end of the phase difference calculation circuit 2-2-2 is connected to the phase difference signal input end of the PID control circuit 2-2-3, and the voltage control signal output end of the PID control circuit 2-2-3 is FPGA control The voltage contr...
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