Hierarchical Checking Method of Layout Data

Abstract

The present application discloses a hierarchical inspection method of layout data, which includes the following steps: Step 1: Select corresponding hierarchical design rules according to the process standards of key dimensions used in layout data. In the second step, all levels are divided into one of mandatory level, identification level, forbidden level, optional level and undefined level in the level design rule. Step 3: Extract the number, name, and physical meaning of the layer used by the layout data from the layout data as the extracted layer usage information. In step 4, compare the extracted layer usage information with the layer information table provided by the IC designer and the layer design rules obtained in step 2. Only when the extracted layer usage information fully complies with the layer design rules can it be determined that the layer inspection is qualified. Otherwise, it is determined that the hierarchical inspection fails. In this application, the level check of the layout is completed by the machine, which greatly improves the work efficiency and ensures the accuracy of the level check.

Description

technical field [0001] The present application relates to a method for checking design rules of an integrated circuit layout. Background technique [0002] Layout verification refers to the use of specialized software tools to verify several items on the layout after wiring to ensure that the layout is completely consistent with the circuit. [0003] Layout verification typically includes: [0004] - design rule check (DRC, design rule check); [0005] - Electrical rule check (ERC, electrical rule check); [0006] - layout and circuit Figure 1 Consistency comparison (LVS, layout versus schematic); [0007] ——layout parasitic parameter extraction (LPE, layout parameter extraction); [0008] - Parasitic resistance extraction (PRE, parasitic resistance extraction). [0009] Among them, DRC and LVS are mandatory verification items, and the rest are optional verification items. [0010] In the DRC stage, the layout data needs to be checked hierarchically to ensure its corr...

AI Technical Summary

Problems solved by technology

Engineers will only review the layout data for individual key layers. Once the missing 2 layers are not reviewed, it will cause layer inspection errors

The integrated circuit manufacturer will carry out the production and manufacturing configuration work according to the layer information table in the follow-up, and the produced integrated circuit chip really misses two layers, which may eventually lead to complete or partial failure of the chip, resulting in huge economic losses

[0017] With the continuous expansion of the scale of integrated circuits and the continuous development of manufacturing processes, the number of layers is increasing. The existing manual layer inspection is very difficult, inefficient, time-consuming and labor-intensive, and there are risks of errors and missed inspections.

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