Formation method of cmos inverter gate

Abstract

The invention discloses a forming method of a grid. The forming method comprises the following steps: providing a substrate, forming a grid material layer, and forming a first strip-shaped structure and a second strip-shaped structure on the grid material layer; forming a first sacrificial layer and a patterned first mask layer, and exposing the patterned first mask layer on the first sacrificial layer on the first strip-shaped structure; then forming a second sacrificial layer, forming a first photoresist with a first window on the second sacrificial layer, wherein the length of the first window is equal to the length of the first photoresist in the direction of width of the grid; etching the first strip-shaped structure along the first window; etching the second strip-shaped structure, wherein the position of a second grid is defined by the etched second strip-shaped structure; etching the grid material layer by taking the etched first strip-shaped structure and the etched second strip-shaped structure as a mask to form the grid. According to the grid formed by the technical scheme, two adjacent first grids on the same column in the direction of the length of the grid are not connected with each other.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a gate of a CMOS inverter. Background technique [0002] With the development of semiconductor technology, it has become possible to fabricate high-level integrated circuits. In order to improve the integration of the circuit, on the one hand, the critical dimension of the semiconductor device is reduced as much as possible to reduce the area occupied by a single semiconductor device; on the other hand, the distance between two adjacent devices is reduced as much as possible. [0003] The formation of a gate in a CMOS inverter is taken as an example for description. [0004] refer to figure 1 , providing substrate 1. [0005] refer to figure 2 , forming a gate material layer 2 on the substrate 1 . [0006] refer to image 3 , and a hard mask layer 3 is formed on the gate material layer 2 . [0007] refer to Figure 4A and Figure 4B , and a first patte...

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Problems solved by technology

[0020] refer to Figure 7B However, since the area of ​​the window 61 is too small, when the photoresist 6 with the window 61 is formed by exposure and development, the shape of the window 61 is easily deformed, and the residue generated during the development is easy to adhere to the window 61

When etching the strip-shaped hard mask 31 through the window 61, it is easy to cause incomplete etching

Then using the patterned hard mask layer 32 as a mask, when etching the gate material layer 2, the formed gates 22 may be connected to each other, resulting in failure of the formed CMOS inverter.

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